scholarly journals On reducing register pressure and energy in multiple-banked register files

2004 ◽  
Author(s):  
J. Abella ◽  
A. Gonzalez
Keyword(s):  
Register Files ◽  
Register Pressure

scholarly journals Early Periodic Register Allocation on ILP Processors

2004 ◽  
Vol 14 (02) ◽  
pp. 287-313 ◽  
Author(s):  
Sid-Ahmed-Ali TOUATI ◽  
Christine EISENBEIS
Keyword(s):  
Optimization Method ◽  
Register Allocation ◽  
Software Pipelining ◽  
Instruction Level Parallelism ◽  
Register Files ◽  
Register Pressure ◽  
Good Improvement ◽  
Level Parallelism ◽  
Register Allocator

Register allocation in loops is generally performed after or during the software pipelining process. This is because doing a conventional register allocation as a first step without assuming a schedule lacks the information of interferences between values live ranges. Thus, the register allocator may introduce an excessive amount of false dependences that dramatically reduce the ILP (Instruction Level Parallelism). We present a new theoretical framework for controlling the register pressure before software pipelining. Thus is based on inserting some anti-dependence edges (register reuse edges) labeled with reuse distances, directly on the data dependence graph. In this new graph, we are able to fix the register pressure, measured as the number of simultaneously alive variables in any schedule. The determination of register and distance reuse is parameterized by the desired minimum initiation interval (MII) as well as by the register pressure constraints - either can be minimized while the other one is fixed. After scheduling, register allocation is done on conventional register sets or on rotating register files. We give an optimal exact model, and an approximation that generalizes the Ning-Gao [22] buffer optimization method. We provide experimental results which show good improvement compared to [22]. Our theoretical model considers superscalar, VLIW and EPIC/IA64 processors.

Code scheduling for VLIW/superscalar processors with limited register files

1992 ◽  
Vol 23 (1-2) ◽  
pp. 197-201
Author(s):  
Tokuzo Kiyohara ◽  
John C. Gyllenhaal
Keyword(s):  
Superscalar Processors ◽  
Register Files ◽  
Code Scheduling

Application Of Elastic Layers To Register Pressure Field On The Model Surface In Supersonic Flow

2016 ◽  
Vol 11 (1) ◽  
pp. 23-33
Author(s):  
Maxim Golubev ◽  
Andrey Shmakov
Keyword(s):  
Surface Waves ◽  
High Frequency ◽  
High Speed ◽  
Pressure Pulsation ◽  
Pressure Field ◽  
Leading Edge ◽  
Supersonic Wind Tunnel ◽  
Register Pressure ◽  
Elastic Layers ◽  
Sharp Leading Edge

The work presents the results of application of panoramic interferential technique which is based on elastic layers (sensors) usage to obtain pressure distribution on the flat plate having sharp leading edge. Experiments were done in supersonic wind tunnel at Mach number M = 4. Sensitivity and response time are shown to be enough to register pressure pulsation against standing and traveling sensor surface waves. Applying high-frequency image acquiring is demonstrated to make possible to distinguish at visualization images high-speed disturbances propagating in the boundary layer from low-speed surface waves

Area and Timing Estimation in Register Files Using Neural Networks

2012 ◽  
Vol 03 (03) ◽  
pp. 269-277
Author(s):  
Assim Sagahyroon ◽  
Jamal Abdalla
Keyword(s):  
Neural Networks ◽  
Timing Estimation ◽  
Register Files

scholarly journals Research of Register Pressure Aware Loop Unrolling Optimizations for Compiler

2018 ◽  
Vol 228 ◽  
pp. 03008
Author(s):  
Xuehua Liu ◽  
Liping Ding ◽  
Yanfeng Li ◽  
Guangxuan Chen ◽  
Jin Du
Keyword(s):  
Finite Number ◽  
Infinite Number ◽  
Performance Degradation ◽  
Transformation Process ◽  
Fine Grained ◽  
Loop Unrolling ◽  
Average Improvement ◽  
Register Pressure ◽  
Linpack Benchmark ◽  
Loop Optimizations

Register pressure problem has been a known problem for compiler because of the mismatch between the infinite number of pseudo registers and the finite number of hard registers. Too heavy register pressure may results in register spilling and then leads to performance degradation. There are a lot of optimizations, especially loop optimizations suffer from register spilling in compiler. In order to fight register pressure and therefore improve the effectiveness of compiler, this research takes the register pressure into account to improve loop unrolling optimization during the transformation process. In addition, a register pressure aware transformation is able to reduce the performance overhead of some fine-grained randomization transformations which can be used to defend against ROP attacks. Experiments showed a peak improvement of about 3.6% and an average improvement of about 1% for SPEC CPU 2006 benchmarks and a peak improvement of about 3% and an average improvement of about 1% for the LINPACK benchmark.

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