Code scheduling for VLIW/superscalar processors with limited register files

Tokuzo Kiyohara; John C. Gyllenhaal

doi:10.1145/144965.145802

Code scheduling for VLIW/superscalar processors with limited register files

ACM SIGMICRO Newsletter ◽

10.1145/144965.145802 ◽

1992 ◽

Vol 23 (1-2) ◽

pp. 197-201

Author(s):

Tokuzo Kiyohara ◽

John C. Gyllenhaal

Keyword(s):

Superscalar Processors ◽

Code Scheduling

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Code Scheduling For Vliw/superscalar Processors With Limited Register Files

[1992] Proceedings the 25th Annual International Symposium on Microarchitecture MICRO 25 ◽

10.1109/micro.1992.697017 ◽

2005 ◽

Cited By ~ 3

Author(s):

T. Kiyohara ◽

J.C. Gyllenhaal

Keyword(s):

Superscalar Processors ◽

Code Scheduling

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Reducing operand transport complexity of superscalar processors using distributed register files

Proceedings 21st International Conference on Computer Design ◽

10.1109/iccd.2003.1240951 ◽

2004 ◽

Cited By ~ 4

Author(s):

S. Bunchua ◽

D.S. Wills ◽

L.M. Wills

Keyword(s):

Superscalar Processors ◽

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High-bandwidth data memory systems for superscalar processors

ACM SIGARCH Computer Architecture News ◽

10.1145/106975.106980 ◽

1991 ◽

Vol 19 (2) ◽

pp. 53-62 ◽

Cited By ~ 1

Author(s):

Gurindar S. Sohi ◽

Manoj Franklin

Keyword(s):

Memory Systems ◽

Superscalar Processors ◽

Data Memory ◽

High Bandwidth

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High-bandwidth data memory systems for superscalar processors

ACM SIGPLAN Notices ◽

10.1145/106973.106980 ◽

1991 ◽

Vol 26 (4) ◽

pp. 53-62 ◽

Cited By ~ 3

Author(s):

Gurindar S. Sohi ◽

Manoj Franklin

Keyword(s):

Memory Systems ◽

Superscalar Processors ◽

Data Memory ◽

High Bandwidth

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A compiler optimization to reduce soft errors in register files

Proceedings of the 2009 ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems - LCTES '09 ◽

10.1145/1542452.1542459 ◽

2009 ◽

Cited By ~ 11

Author(s):

Jongeun Lee ◽

Aviral Shrivastava

Keyword(s):

Compiler Optimization ◽

Soft Errors ◽

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Power-aware code scheduling for clusters of active disks

ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005. ◽

10.1109/lpe.2005.195530 ◽

2005 ◽

Author(s):

S.W. Son ◽

G. Chen ◽

M. Kandemir

Keyword(s):

Code Scheduling ◽

Active Disks

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Instruction distribution heuristics for quad-cluster, dynamically-scheduled, superscalar processors

Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000 ◽

10.1109/micro.2000.898083 ◽

2002 ◽

Cited By ~ 14

Author(s):

A. Baniasadi ◽

A. Moshovos

Keyword(s):

Superscalar Processors

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Area and Timing Estimation in Register Files Using Neural Networks

Circuits and Systems ◽

10.4236/cs.2012.33037 ◽

2012 ◽

Vol 03 (03) ◽

pp. 269-277

Author(s):

Assim Sagahyroon ◽

Jamal Abdalla

Keyword(s):

Neural Networks ◽

Timing Estimation ◽

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Data value speculation in superscalar processors

Microprocessors and Microsystems ◽

10.1016/s0141-9331(98)00086-6 ◽

1998 ◽

Vol 22 (6) ◽

pp. 293-301 ◽

Cited By ~ 3

Author(s):

Jose Gonzalez ◽

Antonio Gonzalez

Keyword(s):

Superscalar Processors ◽

Data Value

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Color-Aware Instructions for Embedded Superscalar Processors

Journal of Signal Processing Systems ◽

10.1007/s11265-010-0497-2 ◽

2010 ◽

Vol 64 (3) ◽

pp. 335-350

Author(s):

Jongmyon Kim ◽

Linda M. Wills ◽

D. Scott Wills

Keyword(s):

Superscalar Processors

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