scholarly journals Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits

2002 ◽  
Author(s):  
P. Heydari ◽  
M. Pedram
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Capacitive Coupling ◽  
Coupling Noise

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Modeling the substrate effect in interconnect line characteristics of high-speed VLSI circuits

1998 ◽  
Vol 46 (10) ◽  
pp. 1436-1443 ◽  
Author(s):  
Jae-Kyung Wee ◽  
Young-June Park ◽  
Hong-Shick Min ◽  
Dae-Hyung Cho ◽  
Man-Ho Seung ◽  
...  
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Substrate Effect

scholarly journals Implementation of time efficient hybrid multiplier for FFT computation

2018 ◽  
Vol 7 (2.7) ◽  
pp. 409 ◽  
Author(s):  
R Nikhil ◽  
G V. S. Veerendra ◽  
J Rahul M. S. Sri Harsha ◽  
Dr V. S. V. Prabhakar
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Chip Area ◽  
Booth Multiplier ◽  
Low Delay ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.  

PERTURBATION TECHNIQUES FOR ON-CHIP LEARNING WITH ANALOGUE VLSI MLPs

1996 ◽  
Vol 06 (02) ◽  
pp. 93-113 ◽  
Author(s):  
GRAHAM CAIRNS ◽  
LIONEL TARASSENKO
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Benchmark Problems ◽  
Perturbation Techniques ◽  
Successful Operation ◽  
Reliable Performance ◽  
Analogue Vlsi ◽  
Computationally Intensive ◽  
On Chip ◽  
Simple Integration

Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions (see Refs. 8 or 13 for example). The use of analogue VLSI allows low power, area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed, making real-time applications possible. In this paper we focus on important issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the issue of weight precision. We first review several perturbation techniques which have been proposed to train multi-layer perceptron (MLP) networks. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measurement hardware for complete on-chip learning systems.

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