Analysis of propagation delays in high-speed VLSI circuits using a distributed line model

1990 ◽  
Vol 9 (8) ◽  
pp. 821-826 ◽  
Author(s):  
M. Passlack ◽  
M. Uhle ◽  
H. Elschner
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Line Model ◽  
Propagation Delays

Modeling the substrate effect in interconnect line characteristics of high-speed VLSI circuits

1998 ◽  
Vol 46 (10) ◽  
pp. 1436-1443 ◽  
Author(s):  
Jae-Kyung Wee ◽  
Young-June Park ◽  
Hong-Shick Min ◽  
Dae-Hyung Cho ◽  
Man-Ho Seung ◽  
...  
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Substrate Effect

scholarly journals Implementation of time efficient hybrid multiplier for FFT computation

2018 ◽  
Vol 7 (2.7) ◽  
pp. 409 ◽  
Author(s):  
R Nikhil ◽  
G V. S. Veerendra ◽  
J Rahul M. S. Sri Harsha ◽  
Dr V. S. V. Prabhakar
Keyword(s):  
Power Efficiency ◽  
High Speed ◽  
Vlsi Circuits ◽  
Low Power Consumption ◽  
Chip Area ◽  
Booth Multiplier ◽  
Low Delay ◽  
Wallace Tree ◽  
Wallace Tree Multiplier ◽  
Carry Save Adders

Now a days in designing a VLSI circuits we are coming across many problems such as high power intake, delay and large utilization of chip area in order to overcome these problems a new architectures are developed. In our project we deals with FFT computation which internally involves series of multiplication and addition therefore requirement of efficient multipliers is needed and therefore we come across two high speed improved multipliers Booth multiplier and Wallace tree multiplier which are good in terms of power efficiency and low output delay. The main aim of our project involves hybridizing the both Wallace multiplier and Booth multiplier which yields low delay and low power consumption than compared to individual multipliers. The Booth multiplier is used for reduction of partial products and for addition operations carry save adders is used in Wallace tree multipliers and thus hybrid is designed by combining both the algorithms which in turn produces better results and they can be observed in comparisons tabular column in our documentation. These multipliers can be designed in many ways such using cmos layout techniques and also using Verilog programming and we have chosen Verilog programming which requires Xilinx software and codes are developed in gate level design model for the respective multiplier models and the results will be tabulated.  

PERTURBATION TECHNIQUES FOR ON-CHIP LEARNING WITH ANALOGUE VLSI MLPs

1996 ◽  
Vol 06 (02) ◽  
pp. 93-113 ◽  
Author(s):  
GRAHAM CAIRNS ◽  
LIONEL TARASSENKO
Keyword(s):  
High Speed ◽  
Vlsi Circuits ◽  
Benchmark Problems ◽  
Perturbation Techniques ◽  
Successful Operation ◽  
Reliable Performance ◽  
Analogue Vlsi ◽  
Computationally Intensive ◽  
On Chip ◽  
Simple Integration

Microelectronic neural network technology has become sufficiently mature over the past few years that reliable performance can now be obtained from VLSI circuits under carefully controlled conditions (see Refs. 8 or 13 for example). The use of analogue VLSI allows low power, area efficient hardware realisations which can perform the computationally intensive feed-forward operation of neural networks at high speed, making real-time applications possible. In this paper we focus on important issues for the successful operation and implementation of on-chip learning with such analogue VLSI neural hardware, in particular the issue of weight precision. We first review several perturbation techniques which have been proposed to train multi-layer perceptron (MLP) networks. We then present a novel error criterion which performs well on benchmark problems and which allows simple integration of error measurement hardware for complete on-chip learning systems.

Bipolar device technology challenge and opportunity

1985 ◽  
Vol 63 (6) ◽  
pp. 683-692 ◽  
Author(s):  
H. D. Barber
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Low Cost ◽  
Chemical Vapor ◽  
Low Noise ◽  
Isolation Techniques ◽  
Propagation Delays ◽  
Technological Barriers ◽  
On Chip ◽  
Bipolar Device

Silicon bipolar device technologies provided 65% of the world's integrated circuits in 1983. Where low noise, high current, low or high voltage, high speed or low cost are required, bipolar technologies are used. This paper will review the present status of bipolar device technologies, which make possible 100-ps gate-propagation delays, 150-μm2 gate areas, 1-GHz bandwidth amplifiers, on-chip control of over 1-A, 350-V operation, 14-GHz fT's and 10-ns. analogue-to-8-bit digital conversion. These devices are realized because of advances in isolation techniques, chemical-vapor deposition, photolithography, diffusion, ion implantation, conductor–contact interconnection technology, etching processes, and materials preparation. This paper will discuss some of the fundamental problems, modelling difficulties, and technological barriers that will impact the future development of bipolar integrated circuits.

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