The role of synthesis in an ASIC design environment

2003 ◽  
Author(s):  
J.R. Fox ◽  
D. Pastorello
Keyword(s):  
Design Environment ◽  
Asic Design

The CMOS gate forest: an efficient and flexible high-performance ASIC design environment

10.1109/4.999 ◽  
1988 ◽  
Vol 23 (2) ◽  
pp. 387-399 ◽  
Author(s):  
M.A. Beunder ◽  
J.P. Kernhof ◽  
B. Hoefflinger
Keyword(s):  
High Performance ◽  
Design Environment ◽  
Asic Design

The Role of Mereotopology and SWRL Rules to Represent Joint Topology Information for Design Collaboration

2008 ◽  
Author(s):  
Kyoung-Yun Kim ◽  
Hyungjeong Yang
Keyword(s):  
Semantic Web ◽  
Physical Structure ◽  
Engineering Properties ◽  
Design Environment ◽  
Joint Design ◽  
Design Collaboration ◽  
Rule Languages ◽  
Topology Information ◽  
Conversion Rules

This paper discusses the role of mereotopology and SWRL (Semantic Web Rule Language) to represent joint topology. Within the physical structure of engineered products, joints are inevitable because of the limitations of component geometries and the required engineering properties. While joints themselves may have similar geometrical configurations, the physical implications of the selected joining processes vary significantly. Mereotopology provides a formal region-based theory for parts and associated concepts. The mereotopologically defined joints topologies are implemented in SWRL (Semantic Web Rule Languages) to overcome the lack of universality of semantic definitions. The paper also presents the conversion rules to translate the mereotopological joint definitions to SWRL rules. These rules can be reasoned for software agents to understand the different joint topologies. This contribution is illustrated by using a real fixture assembly. Also, the remaining challenges to realize a semantic assembly joint design environment are discussed in this paper.

scholarly journals PEMBERDAYAAN MASYARAKAT DALAM MENJAGA KEBERSIHAN SUNGAI MELALUI PENGGUNAAN TEMPAT SAMPAH TERAPUNG ( FLOATING TRASH CAN ) DI DESA TANJUNG SETEKO KECAMATAN INDRALAYA KABUPATEN OGAN ILIR

2014 ◽  
Vol 2 (1) ◽  
pp. 63-68
Author(s):  
Nukmal Hakim
Keyword(s):  
Community Service ◽  
Target Audience ◽  
Design Environment ◽  
Service Activities ◽  
The Village ◽  
Alternative Solutions

Empowerment have keeping the River Health  by using the Float Trash Can in Tanjung Seteko Village Indralaya sub distric Ogany Ilir Regency.  Provide alternative solutions that could be applied in order to overcome the bad habits people taking out the trash into the river. Maintenance of order and cleanliness of the river tributaries in the village of Tanjung Seteko Indralaya District . This activities are expected to provide tangible benefits to the target audience , as: 1 ) . Society has a floating trash . 2 ) . Society will be protected from various diseases caused by waste dumped into the river . The Community Service activities consciousness will arise to always maintain the cleanliness of the river , Trash Floating  is one of the main of the solution in addressing the problems of waste in the water , floating trash can is a design environment technology in the form of floating garbage which is applied through simple methods and technologies to optimize the role of communities around the river in South Indralaya to get used to dispose of waste in place and eliminate bad habits not to throw garbage into the river.

scholarly journals Exploration of dual supply voltage logic synthesis in state-of-the-art ASIC design flows

2003 ◽  
Vol 1 ◽  
pp. 185-189
Author(s):  
T. Mahnke ◽  
W. Stechele ◽  
M. Embacher ◽  
W. Hoeld
Keyword(s):  
Power Optimization ◽  
Supply Voltage ◽  
State Of The Art ◽  
Logic Synthesis ◽  
Design Environment ◽  
New Approach ◽  
Cell Library ◽  
Asic Design ◽  
Synthesis Methodology ◽  
Basic Evaluation

Abstract. Dual supply voltage scaling (DSVS) for logiclevel power optimization at the has increasingly attracted attention over the last few years. However, mainly due to the fact that the most widely used design tools do not support this new technique, it has still not become an integral part of real-world design flows. In this paper, a novel logic synthesis methodology that enables DSVS while relying entirely on standard tools is presented. The key to this methodology is a suitably modeled dual supply voltage (DSV) standard cell library. A basic evaluation of the methodology has been carried out on a number of MCNC benchmark circuits. In all these experiments, the results of state-of-the-art powerdriven single supply voltage (SSV) logic synthesis have been used as references in order to determine the true additional benefit of DSVS. Compared with the results of SSV power optimization, additional power reductions of 10% on average have been achieved. The results prove the feasibility of the new approach and reveal its greater efficiency in comparison with a well-known dedicated DSVS algorithm. Finally, the methodology has been applied to an embedded microcontroller core in order to further explore the potentials and limitations of DSVS in an existing industrial design environment.

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