Leakage power estimation for deep submicron circuits in an ASIC design environment

Proceedings of ASP-DAC/VLSI Design 2002. 7th Asia and South Pacific Design Automation Conference and 15h International Conference on VLSI Design ◽

10.1109/aspdac.2002.994883 ◽

2003 ◽

Cited By ~ 13

Author(s):

R. Kumar ◽

C.P. Ravikumar

Keyword(s):

Power Estimation ◽

Deep Submicron ◽

Leakage Power ◽

Design Environment ◽

Asic Design ◽

Deep Submicron Circuits

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Dynamic power estimation for deep submicron circuits with process variation

2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC) ◽

10.1109/aspdac.2010.5419818 ◽

2010 ◽

Cited By ~ 8

Author(s):

Quang Dinh ◽

Deming Chen ◽

Martin D. F. Wong

Keyword(s):

Process Variation ◽

Power Estimation ◽

Deep Submicron ◽

Dynamic Power ◽

Deep Submicron Circuits

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The CMOS gate forest: an efficient and flexible high-performance ASIC design environment

IEEE Journal of Solid-State Circuits ◽

10.1109/4.999 ◽

1988 ◽

Vol 23 (2) ◽

pp. 387-399 ◽

Cited By ~ 21

Author(s):

M.A. Beunder ◽

J.P. Kernhof ◽

B. Hoefflinger

Keyword(s):

High Performance ◽

Design Environment ◽

Asic Design

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System-Level Leakage Power Estimation Model for ASIC Designs

Advances in Electrical and Electronic Engineering ◽

10.15598/aeee.v16i3.2947 ◽

2018 ◽

Vol 16 (3) ◽

Author(s):

Abhishek Narayan Tripathi ◽

Arvind Rajawat

Keyword(s):

Power Estimation ◽

Leakage Power ◽

System Level ◽

Estimation Model

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Leakage power estimation and minimization in configurable logic block of FPGA

2008 International Conference on Computer and Communication Engineering ◽

10.1109/iccce.2008.4580610 ◽

2008 ◽

Author(s):

A. K. Kureshi ◽

Mohd. Hasan

Keyword(s):

Power Estimation ◽

Leakage Power ◽

Logic Block

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Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - Lecture Notes in Computer Science ◽

10.1007/978-3-642-24154-3_18 ◽

2011 ◽

pp. 173-179 ◽

Cited By ~ 1

Author(s):

Alireza Khosropour ◽

Hossein Aghababa ◽

Ali Afzali-Kusha ◽

Behjat Forouzandeh

Keyword(s):

Extreme Value Distribution ◽

Power Estimation ◽

Extreme Value ◽

Leakage Power ◽

Value Distribution ◽

Generalized Extreme Value Distribution ◽

Generalized Extreme Value

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Leakage Power Reduction in Deep Submicron VLSI Circuits Using Delay-Based Power Gating

National Academy Science Letters ◽

10.1007/s40009-019-00848-4 ◽

2019 ◽

Vol 43 (3) ◽

pp. 229-232 ◽

Cited By ~ 1

Author(s):

T. Thamaraimanalan ◽

P. Sampath

Keyword(s):

Deep Submicron ◽

Power Reduction ◽

Leakage Power ◽

Vlsi Circuits ◽

Power Gating

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WTA - Waveform-based Timing Analysis for deep submicron circuits

IEEE/ACM International Conference on Computer Aided Design, 2002. ICCAD 2002. ◽

10.1109/iccad.2002.1167598 ◽

2003 ◽

Cited By ~ 3

Author(s):

L. McMurchie ◽

C. Sechen

Keyword(s):

Timing Analysis ◽

Deep Submicron ◽

Deep Submicron Circuits

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Runtime leakage power estimation technique for combinational circuits

2007 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2007.358062 ◽

2007 ◽

Cited By ~ 4

Author(s):

Yu-Shiang Lin ◽

Dennis Sylvester

Keyword(s):

Power Estimation ◽

Leakage Power ◽

Estimation Technique ◽

Combinational Circuits

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The role of synthesis in an ASIC design environment

Proceedings 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors ◽

10.1109/iccd.1989.63365 ◽

2003 ◽

Cited By ~ 1

Author(s):

J.R. Fox ◽

D. Pastorello

Keyword(s):

Design Environment ◽

Asic Design

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EMI-noise analysis under ASIC design environment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.892857 ◽

2000 ◽

Vol 19 (11) ◽

pp. 1337-1346 ◽

Cited By ~ 18

Author(s):

S. Hayashi ◽

M. Yamada

Keyword(s):

Noise Analysis ◽

Design Environment ◽

Asic Design

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