New test compression scheme based on low power BIST

2013 ◽  
Author(s):  
J. Tyszer ◽  
M. Filipek ◽  
G. Mrugalski ◽  
N. Mukherjee ◽  
J. Rajski
Keyword(s):  
Low Power ◽  
Compression Scheme ◽  
Test Compression

Low Power Test Compression with Programmable Broadcast-Based Control

2014 ◽  
Author(s):  
Sylwester Milewski ◽  
Grzegorz Mrugalski ◽  
Janusz Rajski ◽  
Jerzy Tyszer
Keyword(s):  
Low Power ◽  
Power Test ◽  
Test Compression ◽  
Low Power Test

Low-Power Scan Operation in Test Compression Environment

2009 ◽  
Vol 28 (11) ◽  
pp. 1742-1755 ◽  
Author(s):  
D. Czysz ◽  
M. Kassab ◽  
Xijiang Lin ◽  
G. Mrugalski ◽  
J. Rajski ◽  
...  
Keyword(s):  
Low Power ◽  
Test Compression

HardCompress: A Novel Hardware-based Low-power Compression Scheme for DNN Accelerators

2021 ◽  
Author(s):  
Ayush Arunachalam ◽  
Shamik Kundu ◽  
Arnab Raha ◽  
Suvadeep Banerjee ◽  
Suriyaprakash Natarajan ◽  
...  
Keyword(s):  
Low Power ◽  
Compression Scheme

Low-Power Programmable PRPG With Test Compression Capabilities

2015 ◽  
Vol 23 (6) ◽  
pp. 1063-1076 ◽  
Author(s):  
Michal Filipek ◽  
Grzegorz Mrugalski ◽  
Nilanjan Mukherjee ◽  
Benoit Nadeau-Dostie ◽  
Janusz Rajski ◽  
...  
Keyword(s):  
Low Power ◽  
Test Compression

Design of Advanced High Performance Bus Tracer in System on Chip Using Matrix Based Compression for Low Power Applications

2020 ◽  
Vol 17 (4) ◽  
pp. 1852-1856
Author(s):  
P. Bhuvaneshwari ◽  
T. R. Jaya Chandra Lekha
Keyword(s):  
Low Power ◽  
High Performance ◽  
Performance Monitoring ◽  
Low Cost ◽  
System On Chip ◽  
Consumer Electronics ◽  
Compression Scheme ◽  
Control Signals ◽  
And Performance ◽  
On Chip

This project proposes multilayer advanced high-performance bus architecture for low power applications. The proposed AHB architecture consists of the bus arbiter and the bus tracer (A.R.M.A., 1999. Specification (Rev 2.0) ARM IHI0011A). The bus arbiter, which is self motivated selects the input packet based on the control signals of the incoming packet. So that arbitration leads to a maximum performance. The On-Chip bus is an important system-on-chip infrastructure that connects major hardware components. Monitoring the on-chip bus signals is crucial to the SoC debugging and performance analysis/optimization (Gu, R.T., et al., 2007. A Low Cost Tile-Based 3D Graphics Full Pipeline with Real-Time Performance Monitoring Support for OpenGL ES in Consumer Electronics. 2007 IEEE International Symposium on Consumer Electronics, June; IEEE. pp.1–6). But, such signals are difficult to observe since they are deeply embedded in a SoC and there are often no sufficient I/O pins to access these signals. Therefore, a straightforward approach is to embed a bus tracer in SoC to capture the bus signal trace and store the trace in on-chip storage such as the trace memory which could then be off loaded to outside world for analysis. The bus tracer is capable of capturing the bus trace with different resolutions, all with efficient built in compression mechanisms such as dictionary based compression scheme for address and control signals and differential compression scheme for data. To improve the compression ratio matrix based compression which is lossless compression is used instead of differential compression. This system is designed using Verilog HDL, simulated using Modelsim and synthesized using Xilinx software.

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