CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

2006 ◽  
Author(s):  
C. Ren ◽  
D. H. Chan ◽  
W. Loh ◽  
J. Peng ◽  
S. Balakumar ◽  
...  
Keyword(s):  
High Temperature ◽  
Metal Gate ◽  
High K ◽  
Cmos Compatible ◽  
Dual Metal

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

2007 ◽  
Vol 51 (11-12) ◽  
pp. 1479-1484 ◽  
Author(s):  
C. Ren ◽  
D.S.H. Chan ◽  
W.Y. Loh ◽  
G.Q. Lo ◽  
N. Balasubramanian ◽  
...  
Keyword(s):  
High Temperature ◽  
Metal Gate ◽  
High K ◽  
Cmos Compatible ◽  
Dual Metal

Improved high-temperature etch processing of high-k metal gate stacks in scaled TANOS memory devices

2010 ◽  
Vol 87 (5-8) ◽  
pp. 1629-1633 ◽  
Author(s):  
J. Paul ◽  
V. Beyer ◽  
M. Czernohorsky ◽  
M.F. Beug ◽  
K. Biedermann ◽  
...  
Keyword(s):  
High Temperature ◽  
Memory Devices ◽  
Gate Stacks ◽  
Metal Gate ◽  
High K

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

Dry Etching of Metal Inserted Poly-Si Stack for Dual High-k and Dual Metal Gate Integration

2018 ◽  
Vol 7 (8) ◽  
pp. P435-P439
Author(s):  
Yongliang Li ◽  
Qiuxia Xu ◽  
Wenwu Wang ◽  
Jing Zhang
Keyword(s):  
Dry Etching ◽  
Metal Gate ◽  
High K ◽  
Dual Metal

High Mobility Dual Metal Gate MOS Transistors with High-k Gate Dielectrics

2004 ◽  
Author(s):  
Kensuke Takahashi ◽  
Kenzo Manabe ◽  
Ayuka Morioka ◽  
Taeko Ikarashi ◽  
Takuya Yoshihara ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
High Mobility ◽  
Mos Transistors ◽  
Metal Gate ◽  
High K ◽  
Dual Metal
Sign in / Sign up

Export Citation Format

Share Document