Impact of Metal Wet Etch on Device Characteristics and Reliability for Dual Metal Gate/High-k CMOS

2006 ◽  
Author(s):  
Zhibo Zhang ◽  
Muhammad Hussain ◽  
Sang Bae ◽  
S. Song ◽  
Byoung Lee
Keyword(s):  
Metal Gate ◽  
High K ◽  
Dual Metal ◽  
Wet Etch

Integration of Dual Metal Gate CMOS on High-k Dielectrics Utilizing a Metal Wet Etch Process

2005 ◽  
Vol 8 (10) ◽  
pp. G271 ◽  
Author(s):  
Zhibo Zhang ◽  
S. C. Song ◽  
Craig Huffman ◽  
Muhammad M. Hussain ◽  
Joel Barnett ◽  
...  
Keyword(s):  
Metal Gate ◽  
High K ◽  
Dual Metal ◽  
Wet Etch

Metal Wet Etch Process Development for Dual Metal Gate CMOS

2005 ◽  
Vol 8 (12) ◽  
pp. G333 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Joel Barnett ◽  
Jason Saulters ◽  
David Baker ◽  
...  
Keyword(s):  
Process Development ◽  
Metal Gate ◽  
Dual Metal ◽  
Wet Etch

Surface Preparations Impact on 248nm Deep UV Photo Resists Adhesion during a Wet Etch

2012 ◽  
Vol 195 ◽  
pp. 58-61 ◽  
Author(s):  
Mathieu Foucaud ◽  
Philippe Garnier ◽  
Vincent Joseph ◽  
Erwine Pargon ◽  
Névine Rochat ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Plasma Etching ◽  
Integration Scheme ◽  
Metal Gate ◽  
Covalent Bonds ◽  
Gate Oxides ◽  
Process Step ◽  
High K ◽  
Lift Off ◽  
Wet Etch

Integrated circuits manufacturing still requires several wet etching operations in presence of photo resist. They are usually used to define the gate oxides or metal in a high k metal gate, gate first integration scheme. During this process step, the resist is used for masking and prevents the underneath material from being etched away. Wet treatments are preferred to plasma etching to perform this operation. Indeed, a smooth channels surface is mandatory to obtain a high carriers mobility. It is then critical to avoid any resist lift-off during the wet treatment in order to guarantee the underlying layers integrity. The observation of the lift-off phenomenon (figure 1) points out two possible root causes: 1) a lateral degradation of the covalent bonds at the interface between the polymer and the underlying material, and 2) a vertical resist degradation, due to the penetration of the etching chemicals into the resist down to the underlying material. Previous observations tend to link the lift-off severity to the bake temperature and the oxidation state of the surface on which the resist is coated.

Metal Wet Etch Issues and Effects in Dual Metal Gate Stack Integration

2006 ◽  
Vol 153 (5) ◽  
pp. G389 ◽  
Author(s):  
Muhammad Mustafa Hussain ◽  
Naim Moumen ◽  
Zhibo Zhang ◽  
Baxter F. Womack
Keyword(s):  
Metal Gate ◽  
Gate Stack ◽  
Dual Metal ◽  
Wet Etch

HIGHLY SCALED CMOS DEVICE TECHNOLOGIES WITH NEW STRUCTURES AND NEW MATERIALS

2006 ◽  
Vol 16 (01) ◽  
pp. 147-173
Author(s):  
YANGYUAN WANG ◽  
RU HUANG ◽  
JINFENG KANG ◽  
SHENGDONG ZHANG
Keyword(s):  
Field Effect Transistors ◽  
Silicon Film ◽  
Double Gate ◽  
New Materials ◽  
Metal Gate ◽  
Gate Stack ◽  
Cmos Inverter ◽  
Short Channel ◽  
High K ◽  
Dual Metal

In this paper field effect transistors (FETs) with new materials and new structures are discussed. A thermal robust HfN/HfO 2 gate stack, which can alleviate the confliction between high quality high k material and low EOT, is investigated. EOT of the gate stack can be scaled down to 0.65nm for MOS capacitor and 0.95nm for MOSFET with higher carrier mobility. A new dual metal gate/high k CMOS integration process was demonstrated based on a dummy HfN technique for better high k quality and metal gate integration. Several new double gate FETs are proposed and investigated, including vertical double gate device with an asymmetric graded lightly doped drain (AGLDD) for better short channel behavior, self-aligned electrically separable double gate device for dynamic threshold voltage operation, new 3-D CMOS inverter based on double gate structure and SOI substrate for compact configuration and new full-symmetric DGJFET for 10nm era with greatly relaxed requirement of silicon film thickness and device design simplification.

Dry Etching of Metal Inserted Poly-Si Stack for Dual High-k and Dual Metal Gate Integration

2018 ◽  
Vol 7 (8) ◽  
pp. P435-P439
Author(s):  
Yongliang Li ◽  
Qiuxia Xu ◽  
Wenwu Wang ◽  
Jing Zhang
Keyword(s):  
Dry Etching ◽  
Metal Gate ◽  
High K ◽  
Dual Metal

CMOS compatible dual metal gate integration with successful Vth adjustment on high-k HfTaON by high-temperature metal intermixing

2007 ◽  
Vol 51 (11-12) ◽  
pp. 1479-1484 ◽  
Author(s):  
C. Ren ◽  
D.S.H. Chan ◽  
W.Y. Loh ◽  
G.Q. Lo ◽  
N. Balasubramanian ◽  
...  
Keyword(s):  
High Temperature ◽  
Metal Gate ◽  
High K ◽  
Cmos Compatible ◽  
Dual Metal
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