Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

2008 ◽  
Author(s):  
Vempati Srinivasa Rao ◽  
Xiaowu Zhang ◽  
Ho Soon Wee ◽  
Hnin Wai Yin ◽  
C S Premachandran ◽  
...  
Keyword(s):  
Wafer Level ◽  
Design And Development ◽  
Fine Pitch ◽  
Wafer Level Package ◽  
Low K

Design and Development of Fine Pitch Copper/Low-K Wafer Level Package

2010 ◽  
Vol 33 (2) ◽  
pp. 377-388 ◽  
Author(s):  
Vempati Srinivasa Rao ◽  
Xiaowu Zhang ◽  
Ho Soon Wee ◽  
Ranjan Rajoo ◽  
C S Premachandran ◽  
...  
Keyword(s):  
Wafer Level ◽  
Design And Development ◽  
Fine Pitch ◽  
Wafer Level Package ◽  
Low K

Reliability Assessment and Failure Analysis of G-Helix, a Free-Standing Compliant Off-Chip Interconnect

2009 ◽  
Vol 6 (1) ◽  
pp. 59-65
Author(s):  
Karan Kacker ◽  
Suresh K. Sitaraman
Keyword(s):  
Failure Analysis ◽  
Dielectric Material ◽  
Organic Substrate ◽  
Wafer Level ◽  
Free Standing ◽  
Fine Pitch ◽  
Cross Section Area ◽  
Interconnect Reliability ◽  
Compliant Interconnect ◽  
Low K

Continued miniaturization in the microelectronics industry calls for chip-to-substrate off-chip interconnects that have 100 μm pitch or less for area-array format. Such fine-pitch interconnects will have a shorter standoff height and a smaller cross-section area, and thus could fail through thermo-mechanical fatigue prematurely. Also, as the industry transitions to porous low-K dielectric/Cu interconnect structures, it is important to ensure that the stresses induced by the off-chip interconnects and the package configuration do not crack or delaminate the low-K dielectric material. Compliant free-standing structures used as off-chip interconnects are a potential solution to address these reliability concerns. In our previous work we have proposed G-Helix interconnects, a lithography-based electroplated compliant off-chip interconnect that can be fabricated at the wafer level. In this paper we develop an assembly process for G-Helix interconnects at a 100 μm pitch, identifying the critical factors that impact the assembly yield of such free-standing compliant interconnect. Reliability data are presented for a 20 mm × 20 mm chip with G-Helix interconnects at a 100 μm pitch assembled on an organic substrate and subjected to accelerated thermal cycling. Subsequent failure analysis of the assembly is performed and limited correlation is shown with failure location predicted by finite elements models.

Reliability of Cu/low-k Wafer Level Package (WLP)

2006 ◽  
Author(s):  
Seung Wook Yoon ◽  
D. Wirtasa ◽  
S. Lim ◽  
Jong Ming Ching ◽  
V. Kripesh
Keyword(s):  
Wafer Level ◽  
Wafer Level Package ◽  
Low K
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