A low power switching method with variable comparator reference voltage and split capacitor array for SAR ADC

Author(s):  
Xiaoyong He ◽  
Junliang He ◽  
Min Cai ◽  
Zhaoxia Jing
2019 ◽  
Vol 29 (06) ◽  
pp. 2050086 ◽  
Author(s):  
Yushi Chen ◽  
Yiqi Zhuang ◽  
Hualian Tang

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator.


2013 ◽  
Vol 60 (7) ◽  
pp. 1726-1739 ◽  
Author(s):  
Weibo Hu ◽  
Yen-Ting Liu ◽  
Tam Nguyen ◽  
DonaldY. C. Lie ◽  
Brian P. Ginsburg

2011 ◽  
Vol 4 (3) ◽  
pp. 17-22
Author(s):  
Weibo Hu ◽  
◽  
Donald Y.C. Lie ◽  

VLSI Design ◽  
2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Yan Zhu ◽  
U-Fat Chio ◽  
He-Gong Wei ◽  
Sai-Weng Sin ◽  
Seng-Pan U ◽  
...  

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.


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