A low-power 10-bit 50-MS/s SAR ADC using a parasitic-compensated split-capacitor DAC

2012 IEEE International Symposium on Circuits and Systems ◽

10.1109/iscas.2012.6271470 ◽

2012 ◽

Cited By ~ 9

Author(s):

Wei Guo ◽

Shahriar Mirabbasi

Keyword(s):

Low Power ◽

Sar Adc ◽

Split Capacitor

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A 8KHz-Bandwidth 13.7bit-ENOB Low-Power Noise-Shaping SAR ADC Using Split-Capacitor DAC

10.1109/icicm54364.2021.9660332 ◽

2021 ◽

Author(s):

Jidong Zhou ◽

Jihai Duan

Keyword(s):

Low Power ◽

Sar Adc ◽

Noise Shaping ◽

Split Capacitor ◽

Power Noise

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A low power switching method with variable comparator reference voltage and split capacitor array for SAR ADC

2016 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC) ◽

10.1109/edssc.2016.7785287 ◽

2016 ◽

Author(s):

Xiaoyong He ◽

Junliang He ◽

Min Cai ◽

Zhaoxia Jing

Keyword(s):

Low Power ◽

Sar Adc ◽

Reference Voltage ◽

Power Switching ◽

Capacitor Array ◽

Split Capacitor ◽

Switching Method

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Design of a high sensitivity and low power ultrasound receiver with a high-resolution SAR ADC for photoacoustic sensing and imaging

10.32657/10356/144400 ◽

2020 ◽

Author(s):

◽

Chuanshi Yang

Keyword(s):

High Resolution ◽

Low Power ◽

High Sensitivity ◽

Sar Adc ◽

Power Ultrasound

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Low Power 10-BIT 8MS/s Asynchronous SAR ADC with Wake-up and Sample Logic for BLE Application

2020 International Conference on Electronics, Information, and Communication (ICEIC) ◽

10.1109/iceic49074.2020.9051214 ◽

2020 ◽

Author(s):

Deeksha Verma ◽

Khuram Shehzad ◽

Sung Jin Kim ◽

Kang-Yoon Lee

Keyword(s):

Low Power ◽

Sar Adc ◽

Asynchronous Sar

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A 0.7-V 0.6- $\mu \text{W}$ 100-kS/s Low-Power SAR ADC With Statistical Estimation-Based Noise Reduction

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.2017.2656138 ◽

2017 ◽

Vol 52 (5) ◽

pp. 1388-1398 ◽

Cited By ~ 35

Author(s):

Long Chen ◽

Xiyuan Tang ◽

Arindam Sanyal ◽

Yeonam Yoon ◽

Jie Cong ◽

...

Keyword(s):

Low Power ◽

Noise Reduction ◽

Statistical Estimation ◽

Sar Adc

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A 10-bit 60-MS/s Low-Power Pipelined ADC With Split-Capacitor CDS Technique

IEEE Transactions on Circuits & Systems II Express Briefs ◽

10.1109/tcsii.2010.2040307 ◽

2010 ◽

Vol 57 (3) ◽

pp. 163-167 ◽

Cited By ~ 19

Author(s):

Jin-Fu Lin ◽

Soon-Jyh Chang ◽

Chun-Cheng Liu ◽

Chih-Hao Huang

Keyword(s):

Low Power ◽

Pipelined Adc ◽

Split Capacitor

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Considerations for Design of High Speed High Resolution Low Power SAR ADC for Direct RF Sampling Receivers

10.1109/icort52730.2021.9581884 ◽

2021 ◽

Author(s):

Amitesh Kumar Tripathi

Keyword(s):

High Resolution ◽

Low Power ◽

High Speed ◽

Sar Adc ◽

Rf Sampling

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Ultra‐low‐voltage low‐power dynamic comparator with forward body bias scheme for SAR ADC

Electronics Letters ◽

10.1049/el.2018.6340 ◽

2018 ◽

Vol 54 (24) ◽

pp. 1370-1372 ◽

Cited By ~ 6

Author(s):

Young‐Ha Hwang ◽

Deog‐Kyoon Jeong

Keyword(s):

Low Power ◽

Low Voltage ◽

Sar Adc ◽

Dynamic Comparator ◽

Power Dynamic ◽

Forward Body Bias ◽

Body Bias

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A 6-Bit Low Power SAR ADC

Communications in Computer and Information Science - Communication, Networks and Computing ◽

10.1007/978-981-13-2372-0_57 ◽

2018 ◽

pp. 642-652

Author(s):

K. Lokesh Krishna ◽

K. Anuradha ◽

Alfakhri M. Murshed

Keyword(s):

Low Power ◽

Sar Adc

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LOW-POWER DYNAMIC COMPARATOR WITH HIGH PRECISION FOR SAR ADC

Turkish Journal of Engineering ◽

10.31127/tuje.625475 ◽

2020 ◽

Author(s):

Ersin Alaybeyoğlu

Keyword(s):

Low Power ◽

High Precision ◽

Sar Adc ◽

Dynamic Comparator ◽

Power Dynamic

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