An 8-bit single-ended ultra-low-power SAR ADC with a novel DAC switching method

2012 ◽  
Author(s):  
Weibo Hu ◽  
Donald Y.C. Lie ◽  
Yen-Ting Liu
Keyword(s):  
Low Power ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Switching Method

An Ultra-Low Power Consumption High-Linearity Switching Scheme for SAR ADC

2019 ◽  
Vol 29 (06) ◽  
pp. 2050086 ◽  
Author(s):  
Yushi Chen ◽  
Yiqi Zhuang ◽  
Hualian Tang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Energy ◽  
Sar Adc ◽  
Low Power Consumption ◽  
Switching Scheme ◽  
Ultra Low Power ◽  
High Linearity ◽  
Common Mode Voltage ◽  
Switching Method

An ultra-low power consumption high-linearity switching scheme for successive approximation register (SAR) analog-to-digital converter (ADC) is presented with a mixed switching method. Based on the combination of C-2C dummy capacitors, the charge sharing technique and monotonic switching method, the proposed switching method achieves high-energy saving and high linearity. Compared with the conventional SAR ADC, the proposed method consumes no reset energy and achieves 98.9% less switching energy and 87.2% reduction in capacitor area. Moreover, the proposed scheme obtains good performance in linearity. Furthermore, the common-mode voltage variation of the proposed scheme is smaller than other published schemes, which is important for decreasing input-dependent offset of the comparator.

An 8-Bit Single-Ended Ultra-Low-Power SAR ADC With a Novel DAC Switching Method and a Counter-Based Digital Control Circuitry

2013 ◽  
Vol 60 (7) ◽  
pp. 1726-1739 ◽  
Author(s):  
Weibo Hu ◽  
Yen-Ting Liu ◽  
Tam Nguyen ◽  
DonaldY. C. Lie ◽  
Brian P. Ginsburg
Keyword(s):  
Low Power ◽  
Digital Control ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Switching Method

A 10-bit Ultra-Low-Power SAR ADC with a Novel DAC Switching Method

2011 ◽  
Vol 4 (3) ◽  
pp. 17-22
Author(s):  
Weibo Hu ◽  
◽  
Donald Y.C. Lie ◽  
Keyword(s):  
Low Power ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Switching Method

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2016 ◽  
pp. 199-228 ◽  
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

scholarly journals A fully integrated RSSI and an ultra-low power SAR ADC for 5.8 GHz DSRC ETC transceiver

2018 ◽  
Vol 86 ◽  
pp. 154-163 ◽  
Author(s):  
Meijuan Zhang ◽  
Ruifeng Liu ◽  
Yuanzhi Zhang ◽  
Wenshen Wang ◽  
Huimin Liu ◽  
...  
Keyword(s):  
Low Power ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Fully Integrated

Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology

Circuit World ◽  
2020 ◽  
Vol 46 (3) ◽  
pp. 183-192
Author(s):  
Muhammad Yasir Faheem ◽  
Shun'an Zhong ◽  
Xinghua Wang ◽  
Muhammad Basit Azeem
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Main Idea ◽  
Cost Effective ◽  
Cmos Technology ◽  
Sar Adc ◽  
Ultra Low Power ◽  
Content Type ◽  
Analogue To Digital

Purpose Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the attention of the researchers. In actual work, there is no mechanism and circuitry for the production of two simultaneous comparator outputs in SAR ADC. Design/methodology/approach A small-sized, low-power and energy-efficient circuitry of a dual comparator and an amplifier is presented, which is the most important part of SAR ADC. The main idea is to design a multi-dimensional circuit which can deliver two quick parallel comparisons. The circuitry of the three devices is combined and miniaturized by introducing a lower number of MOSFET’s and small-sized capacitors in such a way that there is no need for any matching and calibration. Findings The supply voltage of the proposed comparator is 0.7 V with the overall power consumption of 0.257mW. The input and clock frequencies are 5 and 50 MHz, respectively. There is no requirement for any offset calibration and mismatching concerns due to sharing and centralization of spider-latch circuitry. The total offset voltages are 0.13 0.31 mV with 0.3VDD to VDD. All the components are small-sized and miniaturized to make the circuit cost-effective and energy-efficient. The rise and response time of comparator is around 100 ns. SNDR improved from 56 to 65 dB where the input-referred noise of an amplifier is 98mVrms. Originality/value The proposed design has no linear-complexity compared with the conventional comparator in both modes (working and standby); it is ultimately intended and designed for 11-bit SAR ADC. The circuit based on three rapid clock pulses for three different modes includes amplification and two parallel comparisons controlled and switched by a latch named as “spider-latch”.

Signal-Adaptive Analog-to-Digital Converters for ULP Wearable and Implantable Medical Devices

2018 ◽  
pp. 413-443
Author(s):  
Nabi Sertac Artan
Keyword(s):  
Low Power ◽  
Medical Devices ◽  
Sar Adc ◽  
The Other ◽  
Implantable Medical Devices ◽  
Ultra Low Power ◽  
Analog To Digital ◽  
Electrophysiological Signals ◽  
Recent Developments ◽  
Adc Architectures

The mission of this chapter is to introduce the reader the recent developments in the design of ultra-Low Power ADCs for Wearable and Implantable Medical Devices (WIMDs). The focus of this chapter will be on Signal-Adaptive Successive Approximation Register (SAR) ADC architectures and their derivatives, since the majority of the ULP medical devices rely on these architectures. The proposed chapter first provides an overview of the WIMDs, and electrophysiological signals. Then, basic SAR ADCs are introduced followed by the study of adaptive SAR ADCs. The chapter concludes with a brief summary of the other prevalent ADC architecture for WIMDs, namely the Level-Crossing ADCs.

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