Comprehensive Study on 2.5D Package Design for Board-Level Reliability in Thermal Cycling and Power Cycling

2018 ◽  
Author(s):  
Shuai Shao ◽  
Yuling Niu ◽  
Jing Wang ◽  
Ruiyang Liu ◽  
Seungbae Park ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Package Design ◽  
Power Cycling ◽  
Board Level ◽  
Board Level Reliability ◽  
Comprehensive Study

PoP Technology for the Automotive Industry

2014 ◽  
Vol 2014 (1) ◽  
pp. 000081-000085
Author(s):  
Jaimal Williamson ◽  
Kurt Wachtler ◽  
David Chin ◽  
Mike Pierce
Keyword(s):  
Automotive Industry ◽  
Memory Performance ◽  
Automotive Applications ◽  
Defect Level ◽  
Packaging Technology ◽  
Package Design ◽  
Surface Mount ◽  
Board Level ◽  
Performance Surface ◽  
Board Level Reliability

Package-on-Package (PoP) technology has been in production for commercial and portable electronic applications for many years. The key challenge for PoP in automotive applications is meeting the aggressive defect level requirements. The need for PoP has historically been driven by mobile and tablet applications and an increased demand for more processor and memory performance within smaller spaces. With the maturity and excellent historical performance of PoP technology used with TI OMAPTM processor products, PoP can now be introduced as a reliable packaging technology in the automotive industry. This paper will describe the work involved in the enablement of commercial PoP technology into the automotive industry. The challenges and requirements regarding package design, warpage performance, surface mount (SMT) characterization, and board-level reliability (BLR) performance will all be explained.

Optimizing Board Level Reliability of a Novel LGA Package for IoT Applications

2016 ◽  
Vol 2016 (1) ◽  
pp. 000675-000682
Author(s):  
Tara Assi ◽  
Paul Galles ◽  
Andrew Mawer ◽  
Trent Uehling ◽  
Steve Safai
Keyword(s):  
Internet Of Things ◽  
Technology Development ◽  
Bend Testing ◽  
Package Design ◽  
Vast Array ◽  
Thermomechanical Cycling ◽  
Iot Applications ◽  
Board Level ◽  
Board Level Reliability ◽  
Level Performance

Abstract Technology development for Internet of Things applications is growing astronomically, increasing the demand for smaller, faster, and lower power solutions to run and power a vast array of connected machines and objects. The LS1012A is the smallest 64-bit processor on the market today, with a novel 211 LGA package that creates a mechanically robust and space efficient component. However, excellent board level reliability is required in order to meet the various IoT application needs. This study evaluates the board level reliability of the 211 LGA by performing single chamber thermomechanical cycling, monotonic bend testing, and JEDEC drop testing. The objective of this study is to fully optimize the board level performance of the 211 LGA without dramatically altering the package design. Two significant board level changes were applied to achieve significant board level performance, exceeding all projected application uses.

Transient Thermal Analysis for Board-Level Chip-Scale Packages Subjected to Coupled Power and Thermal Cycling Test Conditions

2005 ◽  
Vol 128 (3) ◽  
pp. 281-284 ◽  
Author(s):  
Tong Hong Wang ◽  
Chang-Chi Lee ◽  
Yi-Shao Lai ◽  
Yu-Cheng Lin
Keyword(s):  
Thermal Analysis ◽  
Boundary Conditions ◽  
Thermal Cycling ◽  
Thermal Cycling Test ◽  
Transient Thermal Analysis ◽  
Cycling Test ◽  
Test Conditions ◽  
Power Cycling ◽  
Transient Thermal ◽  
Board Level

In this work, thermal characteristics of a board-level chip-scale package, subjected to coupled power and thermal cycling test conditions defined by JEDEC, are investigated through the transient thermal analysis. Tabular boundary conditions are utilized to deal with time-varying thermal boundary conditions brought by thermal cycling. It is obvious from the analysis that the presence of power cycling leads to a significant deviation of the junction temperature from the thermal cycling profile. However, for components away from the die, the deviation is insignificant. Moreover, for low-power applications, temperature histories from coupled power and thermal cycling are approximately linear combinations of temperature histories from pure power cycling and the ones from pure thermal cycling.

Board-Level Reliability of 3D through Glass via Filters During Thermal Cycling

2016 ◽  
Author(s):  
Scott McCann ◽  
Satoru Kuramochi ◽  
Hobie Yun ◽  
Venkatesh Sundaram ◽  
M. Raj Pulugurtha ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Board Level ◽  
Board Level Reliability

Board Level Power Cycling and Thermal Cycling Fatigue Reliability of Chip-scale Packages

2005 ◽  
Vol 2 (3) ◽  
pp. 171-179 ◽  
Author(s):  
Tong Hong Wang ◽  
Yi-Shao Lai ◽  
Chang-Chi Lee
Keyword(s):  
Thermal Cycling ◽  
Transient Temperature ◽  
Fatigue Reliability ◽  
Mechanical Coupling ◽  
Fine Pitch ◽  
Power Cycling ◽  
Chip Scale Package ◽  
Thermal Cycling Fatigue ◽  
Transient Thermal ◽  
Board Level

In this paper, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, was carried out to investigate board-level fatigue reliability of a thin profile and fine pitch ball grid array (TFBGA) chip-scale package under accelerated power cycling test conditions. Experiments for steady-state and transient thermal dissipations were conducted to verify the thermal analysis. Comparing between numerical results for power cycling and thermal cycling, it is noticed that for the tests with similar low and high temperature extremes, power cycling results in a much longer fatigue life than thermal cycling, which indicates that thermal cycling is a more conservative criterion than power cycling is in evaluating the fatigue resistance of the electronic packages.

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