Ultra-Fine Pitch 3D Integration Using Face-to-Face Hybrid Wafer Bonding Combined with a Via-Middle Through-Silicon-Via Process

2016 ◽  
Author(s):  
Soon-Wook Kim ◽  
Mikael Detalle ◽  
Lan Peng ◽  
Philip Nolmans ◽  
Nancy Heylen ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
3D Integration ◽  
Through Silicon Via ◽  
Face To Face ◽  
Fine Pitch

Face to Face Hybrid Wafer Bonding for Fine Pitch Applications

2020 ◽  
Author(s):  
Daniel W. Fisher ◽  
Sarah Knickerbocker ◽  
Daniel Smith ◽  
Robert Katz ◽  
John Garant ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Face To Face ◽  
Fine Pitch

High Efficiency Single Wafer Cleaning for Wafer Bonding-Based 3D Integration Applications

2012 ◽  
Vol 187 ◽  
pp. 269-272 ◽  
Author(s):  
Don Dussault ◽  
F. Fournel ◽  
V. Dragoi
Keyword(s):  
Removal Efficiency ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Current Work ◽  
Particle Removal ◽  
3D Integration ◽  
Production Scale ◽  
Megasonic Cleaning ◽  
Wafer Cleaning ◽  
Transducer Design

Current work describes development, testing and verification of a single wafer megasonic cleaning method utilizing a transducer design that meets the extreme particle neutrality, Particle Removal Efficiency (PRE), and repeatability requirements of production scale wafer bonding and other applications requiring extremely low particle levels.

Fine‐pitch through‐silicon via integration with self‐aligned back‐side benzocyclobutene passivation layer

2016 ◽  
Vol 11 (10) ◽  
pp. 619-622 ◽  
Author(s):  
Yong Guan ◽  
Shenglin Ma ◽  
Qinghua Zeng ◽  
Jing Chen ◽  
Yufeng Jin
Keyword(s):  
Passivation Layer ◽  
Back Side ◽  
Through Silicon Via ◽  
Fine Pitch

Die to Die and Die To Wafer Bonding Solution for High Density, Fine Pitch Micro-Bumped Die

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 002251-002284 ◽  
Author(s):  
Gilbert Lecarpentier ◽  
Joeri De Vos
Keyword(s):  
Wafer Bonding ◽  
Flip Chip ◽  
High Accuracy ◽  
High Density ◽  
Size Reduction ◽  
Direct Impact ◽  
3 Dimensional ◽  
Fine Pitch ◽  
Placement Accuracy ◽  
Die Bonding

Higher density interconnection using 3-Dimensional technology implies a pitch reduction and the use of micro-bumps. The micro-bump size reduction has a direct impact on the placement accuracy needed on the die placement and flip chip bonding equipment. The paper presents a Die-to-Die and Die-to-Wafer, high accuracy, die bonding solution illustrated by the flip chip assembly of a large 2x2cm die consisting of 1 million 10 μm micro-bumps at 20 μm pitch

Bonding Technologies for 3D integration

2015 ◽  
Vol 2015 (1) ◽  
pp. 000231-000234
Author(s):  
Sascha Lohse ◽  
Alexander Wollanke
Keyword(s):  
Flip Chip ◽  
Process Technology ◽  
3D Integration ◽  
Test Procedures ◽  
Fine Pitch ◽  
Ic Packaging ◽  
Die Stacking ◽  
3D Packaging ◽  
Small Bump ◽  
Suitable Process

Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packaging. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands. Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging. In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 μm) and small bump diameter (down to 13 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.

Scaling Challenges of Semiconductor Packaging in the Era of Big Data

2013 ◽  
Vol 2013 (1) ◽  
pp. 000402-000407 ◽  
Author(s):  
Yasumitsu Orii ◽  
Akihiro Horibe ◽  
Kazushige Toriyama ◽  
Keiji Matsumoto ◽  
Hirokazu Noma ◽  
...  
Keyword(s):  
Big Data ◽  
Material Selection ◽  
Organic Substrate ◽  
Critical Element ◽  
3D Integration ◽  
Technology Innovations ◽  
Fine Pitch ◽  
3D Chip Stacking ◽  
Semiconductor Packaging ◽  
Underfill Material

In advent of multimedia, social media and Internet of Things, our world is exploding with enormous amount of data, so-called Big Data. The use of Big Data provides us with opportunities to bring solutions and innovations to variety of industries such as healthcare, energy, banking and automotive. On the other hand, the computing requirement to analyze this large volume of data is becoming higher than ever. The exascale computing is required in the Era of Big Data. In order to achieve this demand, further technology innovations for package scaling such as 3D-IC with TSV (through silicon via) are needed. The fine pitch die-to-die interconnection is a key element in increasing the total bandwidth in 3D integration. The important technologies in 3D integration include micro-bumping, thermally enhanced underfill materials and advanced interposers. Material selection for reliable fine-pitch interconnection has become a critical challenge in 3D chip stacking. Underfill material in die-to-die device is also a critical element in reducing total packaging stress and in enhancing vertical thermal conductivity. Low CTE high-density organic substrate is an emerging technology for 2.5D structure.

Si Vapor Chamber Integrated with Through Silicon Via for 3D Packaging

2013 ◽  
Vol 2013 (1) ◽  
pp. 000552-000557 ◽  
Author(s):  
Jun Taniguchi ◽  
Takeshi Shioga ◽  
Yoshihiro Mizuno
Keyword(s):  
Thermal Resistance ◽  
Heat Dissipation ◽  
Working Fluid ◽  
In Situ Observation ◽  
Vapor Chamber ◽  
Cover Glass ◽  
Through Silicon Via ◽  
Improvement Rate ◽  
Fine Pitch ◽  
3D Packaging

We demonstrate an etched silicon vapor chamber integrated with a through-silicon via (TSV) for 3D packaging. The Si vapor chamber chip enables low mismatch in the thermal expansion coefficient of a Si-LSI chip and provides a new heat dissipation path for 3D-LSI inter layer cooling. For the first prototype of the vapor chamber, an outside 33-mm × 33-mm chip consisting of a 25-mm × 25-mm area for the vapor chamber, a wick structure 30-μm high, and a vapor passage 100-μm high is developed. In-situ observation of the behavior of the working fluid through the cover glass and heat transfer enhancement is successfully demonstrated. The improvement rate of thermal resistance is 7.1% compared to a test chip without working fluid. Next, the fluid flow of a second vapor chamber prototype consisting of the first prototype integrated with a TSV structure using a Si pillar of 150-μm diameter is investigated. Thermal resistance and droplet observation conducted to evaluate the influence of the TSV. The operation of the vapor chamber is confirmed when a Si pillar is arranged to a coarse pitch of more than 500 μm. A droplet is generated and the vapor passage is partially obstructed. However, the droplet eventually degenerated and the performance of the vapor chamber is maintained. When the Si pillar is arranged to a fine pitch of 200 μm, the entire vapor passage is blocked during the liquid charging process, and no improvement is observed in the thermal resistance of the chip.

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