Experimental thermal characterization and thermal model validation of 3D packages using a programmable thermal test chip

2015 ◽  
Author(s):  
H. Oprins ◽  
V. Cherman ◽  
G. Van der Plas ◽  
F. Maggioni ◽  
J. De Vos ◽  
...  
Keyword(s):  
Model Validation ◽  
Thermal Model ◽  
Thermal Characterization ◽  
Test Chip ◽  
Thermal Test

Stacked Chip Thermal Model Validation using Thermal Test Chips

2012 ◽  
Vol 2012 (1) ◽  
pp. 000873-000881
Author(s):  
Thomas Tarter ◽  
Bernie Siegal
Keyword(s):  
Model Validation ◽  
Thermal Model ◽  
Thermal Test ◽  
Test Chips

Flip Chip Thermal Test Vehicle Design: Requirements, Evaluations, and Validations

2003 ◽  
Author(s):  
Teck Joo Goh ◽  
Chia-Pin Chiu ◽  
K. N. Seetharamu ◽  
G. A. Quadir ◽  
Z. A. Zainal
Keyword(s):  
Flip Chip ◽  
Printed Circuit Board ◽  
Thermal Characterization ◽  
Circuit Board ◽  
Vehicle Design ◽  
Test Chip ◽  
Test Vehicle ◽  
Design Processes ◽  
Thermal Test ◽  
Design Requirements

This paper reviews the design of a flip chip thermal test vehicle. Design requirements for different applications such as thermal characterization, assembly process optimization, and product burn-in simulation are outlined. The design processes of different thermal test chip structures including the temperature sensor and passive heaters are described in detail. In addition, the design of fireball heater, a novel test chip structure used for evaluating the effectiveness of heat spreading of advanced thermal solutions, is also illustrated. The design considerations and processes of the package substrate and printed circuit board with special emphasis on the physical routing of the thermal test chip structures are described. These design processes are supported with thermal data from various finite-element analyses (FEA) carried out to evaluate the capability and limitations of thermal test vehicle design. Design optimization as the outcome of these analyses is also elaborated. Lastly, the validation and calibration procedures of the thermal test vehicle are presented in this paper.

A Scalable Multi-Functional Thermal Test Chip Family: Design and Evaluation

2001 ◽  
Vol 123 (4) ◽  
pp. 323-330 ◽  
Author(s):  
Zs. Benedek ◽  
B. Courtois ◽  
G. Farkas ◽  
E. Kolla´r ◽  
S. Mir ◽  
...  
Keyword(s):  
Temperature Sensor ◽  
Thermal Characterization ◽  
Thermal Engineering ◽  
Test Chip ◽  
Basic Cell ◽  
Thermal Test ◽  
Wide Range ◽  
The Family ◽  
Test Chips

Nowadays, thermal characterization of IC packages and packaging technologies is becoming a key task in thermal engineering. To support this by measurements, we developed a family of thermal test chips that allow a wide range of possible applications. Our chips are based on the same basic cell that is mainly covered by dissipating resistors and also contains a temperature sensor. These basic cells are organized into arrays of different size. The arrays are designed such that further “super arrays” can also be built for tiling up larger package cavities. The first members of the family, TMC9 and TMC81, have been manufactured. Our measurements show that the goals aimed at the design have been achieved.

Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

2017 ◽  
Vol 139 (1) ◽  
Author(s):  
Herman Oprins ◽  
Vladimir Cherman ◽  
Tomas Webers ◽  
Abdellah Salahouelhadj ◽  
Soon-Wook Kim ◽  
...  
Keyword(s):  
Thermal Resistance ◽  
Wafer Bonding ◽  
Three Dimensional ◽  
Measurement Data ◽  
Thermal Characterization ◽  
Test Chip ◽  
Thermal Test ◽  
Wafer Pair ◽  
Transient Measurement

In this paper, we present the design of a passive test chip with thermal test structures in the Metal 1 layer of the back-end of line (BEOL) for the experimental thermal characterization of the intertier thermal resistance of wafer-pairs fabricated by three-dimensional (3D) hybrid Cu/dielectric wafer-to-wafer (W2W) bonding. The thermal test structures include heater elements and temperature sensors. The steady-state or transient measurement data are combined with a modeling study to extract the thermal resistance of the bonded interface for the fabricated bonded wafer pair. The extracted thermal resistance of the die–die interface created by hybrid wafer-to-wafer bonding is compared to literature data for die-to-die (D2D) or die-to-wafer (D2W) stacking with microbumps. The low thermal resistance of the thin bonded dielectric interface indicates that hybrid Cu/dielectric bonding is a promising technology to create 3D chip stacks with a low thermal die-to-die resistance.

Thermal model validation of an electric-driven smart window through experimental data and evaluation of the impact on a case study

2020 ◽  
Vol 181 ◽  
pp. 107134 ◽  
Author(s):  
Giovanni Ciampi ◽  
Michelangelo Scorpio ◽  
Yorgos Spanodimitriou ◽  
Antonio Rosato ◽  
Sergio Sibilio
Keyword(s):  
Experimental Data ◽  
Model Validation ◽  
Thermal Model ◽  
Smart Window ◽  
The Impact
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