Single chip plated Ni/Pd over ALCAP bond pads for flip chip applications and prototyping

2013 ◽  
Author(s):  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
Paul N. Houston ◽  
Fei Xie ◽  
Le Hang La
Keyword(s):  
Flip Chip ◽  
Single Chip ◽  
Bond Pads

Processing, Bumping and Assembly of Single Chip Plated Ni/Pd over ALCAP Bond Pads for Flip Chip Applications and Prototyping

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001841-001869
Author(s):  
Brian J. Lewis ◽  
Daniel F. Baldwin ◽  
Paul N. Houston ◽  
Le hang La ◽  
Tim Spark
Keyword(s):  
Flip Chip ◽  
Process Development ◽  
Single Chip ◽  
Flip Chips ◽  
Chip Technology ◽  
Development Cycle ◽  
Before And After ◽  
Selective Plating ◽  
Bond Pads ◽  
Comprehensive Study

For Designer and Engineers, it is common during the process development cycle for new products to have limitations on the materials that are available for the prototype work. Most SMT devices are readily available in different formats/solder alloys to satisfy most of the needs for passive needs. However, many times IC devices are limited to what is available from the fab or an IC broker. These limitations can mean that die only come in aluminum, wirebond ready I/O metallization or that the silicon wafers already sawn and in single die formats. For applications where advancement in performance or miniaturization is needed, and the benefits of flip chip technology are attractive, then it is not trivial to be able to use these die. In these cases, the process of adding solderable plating technologies to the I/O bond pads is very favorable. The technologies are currently run for wafer lever plating baths, but very little has been done to evaluate single chip plating. Work in plating Ni/Pd onto the ALCAP structure has been performed to evaluate the process and feasibility of processing groups of singulated die with aluminum bond pads. The work to be detailed in this paper will go through the chemistries used in the plating process onto an aluminum bond pad that makes it suitable for flip chip processes. Several bumping structures, such as solder bumping over this plating technology and plating over gold or copper stud bumps, are evaluated. A process for bumping the flip chips is also detailed. The data for shear testing of the 10 variations before and after 500 liquid thermal shock cycles is detailed. Finally, a comprehensive study for assembly of solder bumped flip chips, with the selective plating process, will be detailed as well as a detailed analysis of the TC reliability of this assembly approach. It will be shown that selective Ni/Pd plating onto single, ALCAP bare die can allow for these typical wirebond die can be used in a practical approach solder flip chip process and provide reasonable reliability results when compared to a mainstream, wafer processed, solder bumped flip chip die.

Electrophoretic Deposition of Carbon Nanotubes for Interconnections in Microelectronics

2013 ◽  
Vol 1559 ◽  
Author(s):  
Chiew Keat Lim ◽  
Yadong Wang ◽  
Shixin Wu
Keyword(s):  
Carbon Nanotubes ◽  
Electric Fields ◽  
Electrophoretic Deposition ◽  
Flip Chip ◽  
Low Cost ◽  
Electrical Contacts ◽  
Mechanical And Thermal Properties ◽  
Multi Walled Carbon Nanotubes ◽  
Bond Pads ◽  
Walled Carbon Nanotubes

ABSTRACTCarbon nanotubes (CNTs) have been considered as a promising interconnect material to replace the solder bump used in the flip chip package because of their special electrical, mechanical and thermal properties, which may promote both the performance and reliability of the flip chip packaging. In this paper, electrophoretic deposition (EPD) of CNTs on substrates has been demonstrated for the interconnect application. EPD is a simple, low cost and high throughput process that is capable to produce densely packed film with good homogeneity at low temperature. By altering the electric fields and deposition time during the EPD process, the thickness of the CNTs film could be controlled. In this study, multi-walled carbon nanotubes (MWCNTs) were successfully coated on the various substrates using the EPD method. A highly uniform CNTs microstructure film with thickness over 5 µm was achieved. In addition, the selective depositions of CNTs on the pre-defined bond pads to form CNTs bumps were also accomplished. By employing typical flip-chip bonding technique, high density CNTs bumps were aligned to form a test chip/host substrate interconnects. The electrical conductivity of the CNTs interconnects was carried out using four-point probe measurement. Reliable electrical contacts with linear relationship in the current-voltage (I-V) characteristic suggesting ohmic behaviour were attained. The overall resistances extracted were also relatively low. These superior electrical properties have demonstrated that the CNTs bumps deposited using EPD method is a viable way to serve as an alternative to current metal solder interconnects material such as Sn-Pb alloys. Hence, it offers a promising interconnect application in the quest for device miniaturization in microelectronic industry.

ARCHITECTURE AND DESIGN OF AN 8-BIT FLUX-1 SUPERCONDUCTOR RSFQ MICROPROCESSOR

2002 ◽  
Vol 12 (02) ◽  
pp. 521-529 ◽  
Author(s):  
MIKHAIL DOROJEVETS
Keyword(s):  
Flip Chip ◽  
Clock Frequency ◽  
Single Chip ◽  
Rapid Single Flux Quantum ◽  
Flip Chip Packaging ◽  
Chip Carrier ◽  
5 Ghz ◽  
Architecture And Design ◽  
And Control ◽  
Instruction Memory

The first single-chip superconductor FLUX-1 microprocessor has been designed in the Rapid Single Flux Quantum (RSFQ) logic and fabricated using 4 kA/cm2, 1.75-μm Nb/AlOx/Nb Josephson junction technology as a result of the collaboration between SUNY Stony Brook and TRW, Inc. A FLUX-1 chip represents an 8-bit deeply pipelined microprocessor prototype with a target clock frequency of 17-20 GHz. A new parallel partitioned architecture has been developed in order to tolerate interconnect delays and fill long FLUX-1 processor pipelines with useful instructions. The processor includes the 16 × 32-bit pipelined instruction memory, 8 integer arithmetic-logic units interleaved with 8 registers, the branch unit, and I/O ports for 5-GHz chip-to-chip communication over Nb microstrip lines on a chip carrier. The FLUX-1 instruction set consists of ~25 arithmetic, logical, and control instructions. A FLUX-1 microprocessor chip contains 65,759 Josephson junctions on a 10.6 mm × 13.2 mm die with flip-chip packaging. First FLUX-1 chips fabricated in August 2001 are currently under testing at TRW, Inc.

Microstructure and Reliability of Sputter Deposited Cr-Crcu-Cu thin Films for Flip-Chip Applications

1996 ◽  
Vol 445 ◽  
Author(s):  
Na Zhang ◽  
Mark Mcnicholas ◽  
Neil Colvin
Keyword(s):  
Cross Sections ◽  
Thermal Cycle ◽  
Flip Chip ◽  
Grain Structure ◽  
Transmission Electron ◽  
Alloy Solder ◽  
Solder Balls ◽  
Columnar Grain ◽  
Sputter Deposited ◽  
Bond Pads

AbstractThe Cr‐CrCu‐Cu metal scheme, as a terminal multistructure metallization for flip chip applications, has been investigated utilizing PVD sputter deposition varying the conditions of deposition power and temperature, and film thickness. A modified Controlled Collapse Chip Connection (C4) process was utilized in order to evaluate the aforementioned deposition of the Cr‐CrCu‐Cu multilayers and the effect of film microstructure on the parameters of shear strength and thermal cycle reliability. Thermal cycle reliability results proved to be a function of both the CrCu alloy and the Cu overlayer thickness. Transmission electron microscopy (TEM) cross‐sections of the Cr‐CrCu‐Cu multilayers suggests that the columnar grain structure of the CrCu layer may provide a sacrificial thermal diffusion barrier between the PbSn alloy solder balls and the Al bond pads during the thermal‐cycle tests.

Thermal Performance of an Adhesive Bonded Superconducting Multichip Module (MCM) on a Gifford-McMahon Cryocooler

2011 ◽  
Vol 2011 (1) ◽  
pp. 000683-000689
Author(s):  
Ranjith John ◽  
Vladimir Dotsenko ◽  
Deepnarayan Gupta ◽  
Ajay Malshe
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Experimental Analysis ◽  
Power Dissipation ◽  
Flip Chip ◽  
Multichip Module ◽  
Future Trends ◽  
Test Bed ◽  
Single Chip ◽  
Free Environment

We report the experimental study of the thermal resistance of a flip chip bonded superconducting multichip module (MCM) in a liquid cryogen free environment. A 5×5 mm2 indium-tin bumped superconducting chip was flip chip bonded on a 1×1 cm2 superconducting carrier chip. A non-conductive adhesive was used as an underfill to enhance the robustness of the package. We designed a test bed where the LSCE module was mounted onto the cold head of a Gifford McMahon (GM) cryocooler. The module was conductively cooled down to 4 K and the thermal resistance between the chip and the carrier chip was analyzed. The experimental results showed that for the power dissipation (2 – 5 mW), which is typical for low temperature superconducting electronic LSCE devices, the thermal resistance was 20.1 +/− 1.9 K/W. Thermal model of the current LSCE package was investigated using COMSOL multi-physics. Theoretical estimates showed that for the current package setup the expected thermal resistance of the bump path to be 6.2 K/W. The discrepancy between the model and experimental analysis has been explained due to the presence of voids and inadequate bump contact area. To our knowledge, this is the first such experimental investigation of the thermal performance of adhesive bonded LSCE package on a cryocooler. This experimental analysis is of paramount importance for future trends in single chip and multichip module packaging of LSCE devices.

Coupled Computational Thermal and Mechanical Analysis of a Single Chip Flip Chip Module With Low-k Dielectric Medium

2011 ◽  
Author(s):  
Fahad Mirza ◽  
Thiagarajan Raman ◽  
Saeed Ghalambor ◽  
Ashraf Bastawros ◽  
Dereje Agonafer
Keyword(s):  
Temperature Distribution ◽  
Silicon Dioxide ◽  
Flip Chip ◽  
Equivalent Stress ◽  
Mechanical Analysis ◽  
Dielectric Medium ◽  
Single Chip ◽  
Maximum Equivalent Stress ◽  
Rc Delay ◽  
Low K

Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). While gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnects. Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of Silicon dioxide (k = 3.9) to reduce the capacitive component in the RC delay. Recent research has shown low-k materials to have characteristics such as low mechanical strength and adhesion. In this paper, thermo-mechanical analysis of a single chip flip-chip module (SCM) consisting of a die integrated with low-k dielectric medium, substrate, solder balls, and a printed circuit board (PCB) is performed. The analysis is done in two steps within the ANSYS finite element software to account for thermally induced stresses due to mismatch in thermal expansion coefficient. In the first step, the thermal analysis is carried out to derive the steady state temperature distribution within the package under the imposed power rating. In the second step, the evaluated temperature field is utilized in a coupled thermo-mechanical structural analysis. The developed framework is utilized to study the thermo-mechanical behavior of various low-k dielectrics, wherein the stresses and strain distributions within the chip region are quantified. The analysis has shown no change in the temperature distribution between the base case of Silicon dioxide (SiO2) and low-k materials. The maximum equivalent stress in the package, for all the four dielectric cases (SiO2, polyimide, Hydrogen Silsesquioxane, and Black diamond) is seen in the silicon region of the die and that it does not change with the dielectric materials. However, the maximum equivalent stress in the low-k/metal layers varies with the materials but is always few orders of magnitude less than their corresponding yield strengths. Comparative analysis between Silicon dioxide (SiO2) and different low-k materials will help in identifying the weak spots in low-k dielectric when exposed to standard user environments.

Non-Chemical Solder Bump Removal Technique for Repackaging Flip Chip ICs

2012 ◽  
Author(s):  
Mauri Sutton ◽  
George Geoghegan ◽  
Kenneth Schopen ◽  
Kathleen Kingma ◽  
Steve Castro ◽  
...  
Keyword(s):  
Success Rate ◽  
Flip Chip ◽  
Solder Bump ◽  
Wire Bonding ◽  
Solder Bumps ◽  
Bonding Area ◽  
Probe Card ◽  
Bond Pads ◽  
Removal Technique ◽  
Predictable Condition

Abstract In this paper we will discuss an empirically discovered technique to remove residual solder bumps or remnants using reflow and wicking to a gold plated surface rather than mechanical or chemical means. Extraction of flip chip ICs, for the purpose of repackaging, can leave bond pads in inconsistent and undesirable conditions such as 1) retaining remnants of the solder bumps or 2) damaged or eliminated pad metal caused by acid or mechanical means used to separate the IC from the board. These conditions hinder subsequent wire bonding and probe card use. Though other techniques have been found to be suitable at times, the technique described in this paper consistently leaves the bonding area in an acceptable, more predictable condition, as the bulk of the solder bump material is removed. This lends to a higher wire bonding success rate.

Single chip bumping and reliability for flip chip processes

1999 ◽  
Vol 39 (9) ◽  
pp. 1389-1397 ◽  
Author(s):  
M. Klein ◽  
H. Oppermann ◽  
R. Kalicki ◽  
R. Aschenbrenner ◽  
H. Reichl
Keyword(s):  
Flip Chip ◽  
Single Chip
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