Modeling and experimental study of thin bond line thermal interface material failure

2013 ◽  
Author(s):  
Shidong Li ◽  
Tuhin Sinha ◽  
Taryn J. Davis ◽  
Kamal Sikka ◽  
Paul Bodenweber
Keyword(s):  
Experimental Study ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Material Failure ◽  
Thermal Interface

Using In situ Capacitance Measurements to Monitor the Stability of Thermal Interface Materials in Complex PCB Assemblies

2010 ◽  
Vol 2010 (1) ◽  
pp. 000450-000457
Author(s):  
Michael Gaynes ◽  
Timothy Chainer ◽  
Edward Yarmchuk ◽  
John Torok ◽  
David Edwards ◽  
...  
Keyword(s):  
Thermal Cycle ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Circuit Board ◽  
Large Area ◽  
Voltage Transformer ◽  
Heat Spreader ◽  
Thermal Interface ◽  
Thermal Solution

A thermal solution for an array of voltage transformer modules which are cooled by a large area, common aluminum heat spreader for a high end server was evaluated using an in situ, capacitive bond line thermal measurement technique. The method measures the capacitance of a non-electrically conducting thermal interface material (TIM) between the electronic module and heat spreader to quantify the TIM bond line effective thickness during assembly and operation. The thermal resistance of the TIM has the same geometric dependence as the inverse of capacitance, therefore, the capacitive technique also provided a monitor of the thermal performance of the interface. This technique was applied to measure the bond line in real time during the assembly of the heat spreader to an array of 37 modules mounted on a printed circuit board. The results showed that the target bond lines were not achieved by application of a constant force alone on the heat spreader, and guided an improved assembly process. The mechanical motion of the TIM was monitored in situ during thermal cycling and found to fluctuate systematically from the hot to cold portions of the thermal cycle, either compressing or stretching the TIM respectively. The capacitive bond line trend showed thermal interface degradation vs. cycle count for several modules which was confirmed by disassembly and visual inspection. Areas of depleted TIM ranged as high as 25% of the module area. Several design and material changes were shown to improve the TIM stability. Power cycling tests were run in parallel to the thermal cycle tests to help relate the results to field performance. The capacitance technique enabled the development and verification of a thermal solution for a complex mechanical system early in the development cycle.

Evaluation of Bare Die Chip Reliability Due to Underfill Materials During Mechanical Actuation and Thermal Cycling

2005 ◽  
Author(s):  
Arv Sinha
Keyword(s):  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Bond Line ◽  
Thermal Interface Material ◽  
High Power Density ◽  
The Finite Element Method ◽  
Chip Design ◽  
Thermal Interface ◽  
Ball Grid Arrays ◽  
Mechanical Actuation

Use of underfill materials to encapsulate ball grid arrays (BGAs) or chip scale packages (CSPs) have become very important in increasing the reliability of area array packages [1]. Underfill enhances the reliability of flip-chip devices by distributing the thermo-mechanical stresses [2, 3]. These stresses are generated due to mechanical actuation and coefficient of thermal expansion mismatch (CTE) [3]. They are required due to high power density of the current chip design to achieve fine bond line at the thermal interface material in order to dissipate heat. In this paper, details of reliability assessment using the finite element method and actual test data will be presented and discussed.

Optimization of a Flux-Less Metal Thermal Interface Material by Reflow in a Vacuum Furnace

2011 ◽  
Vol 2011 (1) ◽  
pp. 000929-000937
Author(s):  
Pierino I Zappella ◽  
Paul W Barnes ◽  
David Muhs ◽  
Bruce Wilson
Keyword(s):  
Flip Chip ◽  
Pure Metal ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Vacuum Furnace ◽  
Acceptance Criteria ◽  
Specific Sequence ◽  
Thermal Interface ◽  
Series Of Experiments ◽  
Initial Objective

This paper describes the work performed with a pure metal thermal interface material (TIM) for the sole purpose to improve the transfer of heat from the die to the metal cover case. A flux-less reflow process is employed in order to reflow the indium TIM material. This operation is performed in a vacuum furnace utilizing heat, vacuum, and pressure in a specific sequence in order to wet the metal lid and the backside of the flip chip die. The initial objective was to demonstrate minimal voiding of the TIM and subsequently limited flow out of molten solder from and along the sides of the die. A series of experiments were employed where acceptance criteria is evaluated by a) X-Ray, b) scanning acoustical microscopy (SAM), and c) cross-section. Acceptance criteria consists of 1) indium wetting of both lid to indium interface and indium to silicon interface die, 2) indium bond line (BLT) thickness, 3) lid tilt, and 4) lid shear strength. Acceptance is determined after a subsequent 4X ball grid array (BGA) reflow in a conventional belt reflow furnace with minimal voiding, no popcorn or blistering of the laminate substrate, and TIM thickness and solder flow out at sides of the die within the acceptable limits of the above mentioned criteria.

Comparison of Thermal Performance of Current High-End Thermal Interface Materials

2007 ◽  
Author(s):  
Gamal Refai-Ahmed ◽  
Zhaojuan He ◽  
Ellen Heian ◽  
Ramzi Vincent ◽  
Tim Rude ◽  
...  
Keyword(s):  
Thermal Performance ◽  
Phase Change Materials ◽  
Bond Line ◽  
Heat Sinks ◽  
Thermal Interface Material ◽  
Test Results ◽  
Thermal Interface ◽  
Graphics Processor ◽  
Significant Performance ◽  
Bonding Technology

Reactive NanoTechnologies (RNT) has developed a reactive bonding technology to directly bond silicon dies to heat sinks with indium solder using a reactive multilayered foil. In this new method of bonding, heat is generated locally by exothermic mixing within the multilayered foil. This heat is used to melt indium solder layers to join the dies to the heat sinks. The measured thermal resistance of the resulting solder bond is 4 to 5 K mm2/W (0.006 to 0.008 K in2/W). In addition, the reactive foil also localizes the heat to the interface, thus minimizing residual stress and thermal damage in the components. In this paper we discuss the thermal performance and reliability test results for reactive multilayer bonding with different bond line thicknesses. We also present detailed comparisons of thermal performance between reactive multilayer bonding and other current Thermal Interface Material (TIM) solutions, including polymer-based greases, phase change materials, and low melting metallic alloy. Benchmark tests were done using the graphics processor on an operational video card as a test vehicle. The test results show that the introduction of a reactive multilayer bond as an interface material between the graphics processor and the thermal management device demonstrates significant performance advantages over any of the other current commercially available TIM solutions.

Fatigue life analysis of Sn96.5Ag3.0Cu0.5 solder thermal interface material of a chip-heat sink assembly in microelectronic applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000473-000477
Author(s):  
M. Ekpu ◽  
R. Bhatti ◽  
M.I. Okereke ◽  
K.C. Otiaba
Keyword(s):  
Heat Sink ◽  
Bond Line ◽  
Thermal Interface Material ◽  
Lead Free ◽  
Heat Management ◽  
Sac305 Solder ◽  
Thermal Interface ◽  
Finite Element Software ◽  
Fatigue Life Analysis ◽  
Free Solder

The reliability of microelectronic devices during operation has been a major challenge in recent years. Microelectronics devices will fail if one or more components do not function properly. Thermal interface materials are more likely to fail because of the role they play in heat management. Lead free solders such as SAC305 solder (Sn96.5Ag3.0Cu0.5) have become the thermal materials of interest because of their high thermal conductivity and government legislations on the ban of lead. Ansys finite element software was used for the design and analysis of the microelectronic device studied. The bond line thicknesses of the SAC305 solder thermal interface material were varied from 0.035 mm to 0.175 mm and a thermal load was applied using commercial thermal cycle profile of −40°C to 80°C. The results obtained showed that stresses and strains reduce as the lead free solder thickness increases. The number of cycles to failure and plastic work density increased as the SAC305 solder thickness is increased. This research showed that an increase in SAC305 solder thickness will improve thermal conduction and reliability. However, the solder thickness is limited to the gap between the chip-heat sink surfaces in contact.

scholarly journals Noncured Graphene Thermal Interface Materials for High-Power Electronics: Minimizing the Thermal Contact Resistance

Nanomaterials ◽  
2021 ◽  
Vol 11 (7) ◽  
pp. 1699
Author(s):  
Sriharsha Sudhindra ◽  
Fariborz Kargar ◽  
Alexander A. Balandin
Keyword(s):  
Contact Resistance ◽  
High Power ◽  
Thermal Contact Resistance ◽  
Thermal Contact ◽  
Wide Band ◽  
Thermal Interface Material ◽  
Thermal Interface Materials ◽  
Total Thermal Resistance ◽  
Thermal Interface ◽  
Interface Materials

We report on experimental investigation of thermal contact resistance, RC, of the noncuring graphene thermal interface materials with the surfaces characterized by different degree of roughness, Sq. It is found that the thermal contact resistance depends on the graphene loading, ξ, non-monotonically, achieving its minimum at the loading fraction of ξ ~15 wt %. Decreasing the surface roughness by Sq~1 μm results in approximately the factor of ×2 decrease in the thermal contact resistance for this graphene loading. The obtained dependences of the thermal conductivity, KTIM, thermal contact resistance, RC, and the total thermal resistance of the thermal interface material layer on ξ and Sq can be utilized for optimization of the loading fraction of graphene for specific materials and roughness of the connecting surfaces. Our results are important for the thermal management of high-power-density electronics implemented with diamond and other wide-band-gap semiconductors.

Interfacially engineered liquid-phase-sintered Cu–In composite solders for thermal interface material applications

2014 ◽  
Vol 49 (22) ◽  
pp. 7844-7854 ◽  
Author(s):  
J. Liu ◽  
U. Sahaym ◽  
I. Dutta ◽  
R. Raj ◽  
M. Renavikar ◽  
...  
Keyword(s):  
Liquid Phase ◽  
Thermal Interface Material ◽  
Thermal Interface
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