Pd-coated Cu wire bonding technology: Chip design, process optimization, production qualification and reliability test for high reliability semiconductor devices

2012 ◽  
Author(s):  
Inderjit Singh ◽  
Ivy Qin ◽  
Hui Xu ◽  
Cuong Huynh ◽  
Shin Low ◽  
...  
Keyword(s):  
Process Optimization ◽  
Design Process ◽  
High Reliability ◽  
Semiconductor Devices ◽  
Wire Bonding ◽  
Reliability Test ◽  
Chip Design ◽  
Bonding Technology

scholarly journals Development of high reliability semiconductor devices by copper wire bonding.

1988 ◽  
Vol 27 (4) ◽  
pp. 299-301
Author(s):  
J. Hirota ◽  
Y. Shibutani ◽  
T. Sugimura ◽  
K. Machida ◽  
T. Okuda
Keyword(s):  
High Reliability ◽  
Copper Wire ◽  
Semiconductor Devices ◽  
Wire Bonding ◽  
Copper Wire Bonding

Chip Design Process Optimization Based on Design Quality Assessment

2010 ◽  
Author(s):  
Stefan Häusler ◽  
Jana Blaschke ◽  
Christian Sebeke ◽  
Wolfgang Rosenstiel ◽  
Axel Hahn ◽  
...  
Keyword(s):  
Quality Assessment ◽  
Process Optimization ◽  
Design Process ◽  
Design Quality ◽  
Chip Design

Modeling and Experimental Study of a Wire Clamp for Wire Bonding

2015 ◽  
Vol 137 (1) ◽  
Author(s):  
Fuliang Wang ◽  
Dengke Fan
Keyword(s):  
Experimental Study ◽  
Finite Element ◽  
Energy Conservation ◽  
Design Process ◽  
Gold Wire ◽  
Wire Bonding ◽  
Fe Model ◽  
Amplification Ratio ◽  
Model Studies ◽  
Thermosonic Wire Bonding

A wire clamp is used to grip a gold wire with in 1–2 ms during thermosonic wire bonding. Modern wire bonders require faster and larger opening wire clamps. In order to simplify the design process and find the key parameters affecting the opening of wire clamps, a model analysis based on energy conservation was developed. The relation between geometric parameters and the amplification ratio was obtained. A finite element (FE) model was also developed in order to calculate the amplification ratio and natural frequency. Experiments were carried out in order to confirm the results of these models. Model studies show that the arm length was the major factor affecting the opening of the wire clamp.

Analyze Physical Design Process Using Big Data Tool

2015 ◽  
Vol 7 (2) ◽  
pp. 31-49 ◽  
Author(s):  
Waseem Ahmed ◽  
Lisa Fan
Keyword(s):  
Design Process ◽  
Data Extraction ◽  
Daily Basis ◽  
Physical Design ◽  
Data Repository ◽  
Chip Design ◽  
Asic Design ◽  
Design Engineers ◽  
Statistical Representation ◽  
And Performance

Physical Design (PD) Data tool is designed mainly to help ASIC design engineers in achieving chip design process quality, optimization and performance measures. The tool uses data mining techniques to handle the existing unstructured data repository. It extracts the relevant data and loads it into a well-structured database. Data archive mechanism is enabled that initially creates and then keeps updating an archive repository on a daily basis. The logs information provide to PD tool is a completely unstructured format which parse by regular expression (regex) based data extraction methodology. It converts the input data into the structured tables. This undergoes the data cleansing process before being fed into the operational DB. PD tool also ensures data integrity and data validity. It helps the design engineers to compare, correlate and inter-relate the results of their existing work with the ones done in the past which gives them a clear picture of the progress made and deviations that occurred. Data analysis can be done using various features offered by the tool such as graphical and statistical representation.

Technologies and Trends to Improve Power Electronic Packaging

2011 ◽  
Vol 2011 (1) ◽  
pp. 000430-000437
Author(s):  
M. Schneider-Ramelow ◽  
M. Hutter ◽  
H. Oppermann ◽  
J.-M. Göhre ◽  
S. Schmitz ◽  
...  
Keyword(s):  
High Reliability ◽  
Transient Liquid Phase ◽  
Wire Bonding ◽  
Temperature Cycling ◽  
Material Behavior ◽  
Process Selection ◽  
Chip Surface ◽  
Bonding Parameters ◽  
Strong Trend ◽  
Die Attach

In the realm of power modules a strong trend toward high temperature and high reliability applications can be observed, which entails new technological challenges, especially for the assembly and packaging of power semiconductors. Because of the well known failure mechanisms of established lead-free standard soldering and heavy aluminum wire bonding technologies, such as fatigue and creep of die attach material and wire bonds at thermal cycling, academic and industrial research focuses on more reliable interconnection technologies. A priority is the research of alternative top and bottom side chip interconnection materials or technologies to improve the temperature cycling capability of power chips that are typically assembled on ceramic substrates. The scientific focus is on Ag sintering as die attach and/or heavy ribbon bonding, for example with Al or bi-metal (Al-Cu). Another focus is the material behavior of ribbon bonds in combination with bonding machine improvements (higher bonding parameters, cutting tool). But there are other very promising technologies like transient liquid phase bonding, for example with Cu-Sn or Ag-Sn systems or Cu heavy wire bonding (up to 400 μm wire diameter) or Cu/Al-Bi metal ribbon bonding. Challenges posed by these technologies have to be discussed focusing on materials and process selection and reliability issues. Process temperatures and temperature profiles must be optimized, wire bonding machines and the chip surface structures as well as finish metallizations need to be adapted. This paper will give an overview of alternative power chip interconnection technologies and discuss the challenges related to processing and reliability.

Sign in / Sign up

Export Citation Format

Share Document