Flip chip power cycling system development and lead free bump power cycling reliability

2012 ◽  
Author(s):  
Max K. C. Wu ◽  
H. Y. Pan ◽  
Larry Lin ◽  
Christine Chiu ◽  
Tulip Chou ◽  
...  
Keyword(s):  
Flip Chip ◽  
System Development ◽  
Lead Free ◽  
Power Cycling ◽  
Cycling System

scholarly journals Growth Kinetics of Reaction Layers in Flip Chip Joints with Cu-cored Lead-free Solder Balls

2004 ◽  
Vol 45 (3) ◽  
pp. 754-758 ◽  
Author(s):  
Ikuo Shohji ◽  
Yuji Shiratori ◽  
Hiroshi Yoshida ◽  
Masahiko Mizukami ◽  
Akira Ichida
Keyword(s):  
Growth Kinetics ◽  
Flip Chip ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Balls ◽  
Free Solder ◽  
Kinetics Of Reaction ◽  
Kinetics Of

Practical Application and Analysis of Lead-Free Solder on Chip-On-Flip-Chip SiP for Hearing Aids

2017 ◽  
Vol 2017 (1) ◽  
pp. 000201-000207 ◽  
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Hearing Aids ◽  
Flip Chip ◽  
Failure Modes ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Practical Application ◽  
Surface Mount ◽  
Free Solder ◽  
On Chip

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Considerable amount of defects associated with solder overflow are found on chip-on-flip-chip (COFC) SiP in hearing aids. Through the use of design of experiments (DOE), lead-free solder defect causes on hearing aids application can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components for hearing aid applications. The practical application and analysis of lead-free solder for hearing aids will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types through the DOE process.

Study on electromigration in flip chip lead-free solder connections with 40 μm or 30 μm diameter on thin film ceramic substrates

2015 ◽  
Vol 2015 (1) ◽  
pp. 000799-000805
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Bernd Kandler ◽  
Bernd Burger
Keyword(s):  
Thin Film ◽  
High Stability ◽  
Flip Chip ◽  
Lead Free ◽  
Published Data ◽  
Organic Substrates ◽  
Lead Free Solder ◽  
Ceramic Substrates ◽  
Solder Bumps ◽  
Free Solder

Electromigration comprises one of the processes affecting the long-term reliability of electronic devices; it has therefore been the focus of many investigations in recent years. In regards to flip chip packaging technology, the majority of published data is concerned with electromigration in solder connections to metallized organic substrates. Hardly any information is available in the literature on electromigration in lead-free solder connections on thin film ceramic substrates. This work presents results of a study of electromigration in lead-free (SAC305) flip chip solder bumps with a nominal diameter of 40 μm or 30 μm with a pitch of 100 μm on silicon chips assembled onto thin film Al2O3 ceramic substrates. The under bump metallization (UBM) comprised of a 5 μm thick electroless nickel immersion gold (ENIG) layer directly deposited on the AlCu0.5 trace. The ceramic substrates were metallized using a thin film multilayer (NiCr-Au(1.5 μm)-Ni(2 μm) structure on the top of which wettable areas were produced with high precision by depositing flash Au (60 nm) of the required diameter (40 μm or 30 μm). All electromigration tests were performed at the temperature of 125 °C. Initially, one chip assembly with 40 μm and one with 30 μm solder bumps was loaded with the current density of 8 kA/cm2 for 1,000 h. The assemblies did not fail and an investigation with SEM revealed no significant changes to the microstructure of the bumps. Thereafter seven chip assemblies with 40 μm solder bumps and five assemblies with 30 μm bumps were subjected to electromigration tests of 14 kA/cm2 or 25 kA/cm2, respectively. Six of the 40 μm-assemblies failed after 7,000 h and none of the 30 μm-assemblies failed after 2,500 h of test duration so far. Investigation of failed samples performed with SEM and EDX showed asymmetric changes of microstructure in respect to current flow. Several intermetallic phases were found to form in the solder. The predominant damage of the interconnects was found to occur at the cathode contact to chip; the Ni-P layers there showed typical columnar Kirkendall voids caused by migration of Ni from the layers into the solder. Failure of the contacts apparently occurred at the interface between Ni-P and solder. In summary, the results of the study indicate a very high stability of lead-free solder connections on ceramic substrates against electromigration. This high stability is primarily due to a better heat dissipation and thus to a relatively low temperature increase of the ceramic packages caused by resistive heating during flow of electric current. In addition, the type of the metallization used in the study seems to be more resistant to electromigration than the standard PCB metallization as it does not contain a copper layer.

C4 EM and CPI Reliability Benefits and Process Challenges of FBEOL Integration Changes Implemented in Lead-free C4 Products

2015 ◽  
Vol 2015 (1) ◽  
pp. 000787-000792
Author(s):  
E. Misra ◽  
T. Wassick ◽  
I. Melville ◽  
K. Tunga ◽  
D. Questad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flip Chip ◽  
Process Integration ◽  
Semiconductor Industry ◽  
Lead Free ◽  
Solder Interconnects ◽  
Design Changes ◽  
Modeling Data ◽  
Free Solder ◽  
Low K

The introduction of low-k & ultra-low-k dielectrics, lead-free (Pb-free) solder interconnects or C4's, and organic flip-chip laminates for integrated circuits have led to some major reliability challenges for the semiconductor industry. These include C4 electromigration (EM) and mechanical failures induced with-in the Si chip due to chip-package interactions (CPI). In 32nm technology, certain novel design changes were evaluated in the last Cu wiring level and the Far Back End of Line levels (FBEOL) to strategically re-distribute the current more uniformly through the Pb-free C4 bumps and therefore improve the C4 EM capabilities of the technology. FBEOL process integration changes, such as increasing the thickness of the hard dielectric (SiNx & SiOx) and reducing the final via diameter, were also evaluated for reducing the mechanical stresses in the weaker BEOL levels and mitigating potential risks for mechanical failures within the Si chip. The supporting white-bump, C4 EM and electrical/mechanical modeling data that demonstrates the benefits of the design and integration changes will be discussed in detail in the paper. Some of the key processing and integration challenges observed due to the design and process updates and the corresponding mitigation steps taken will also be discussed.

Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Comparative Modeling and Analysis of Lead-Free Solder Extrusion for the Design of Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000111-000116
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Design Of Experiments ◽  
Flip Chip ◽  
Failure Modes ◽  
Form Factors ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Modeling And Analysis ◽  
Surface Mount ◽  
Free Solder

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Through the use of design of experiments (DOE), lead-free solder defect causes can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components. The systematic investigation will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types utilizing the design of experiments methods.

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