Challenge of vacuum molded flip chip packaging technology

2nd International IEEE Conference on Polymers and Adhesives in Microelectronics and Photonics POLYTRONIC 2002 Conference Proceedings (Cat No 02EX599) POLYTR-02 ◽

10.1109/polytr.2002.1020218 ◽

2003 ◽

Cited By ~ 4

Author(s):

K. Chai ◽

E. Wu ◽

J.Y. Tong

Keyword(s):

Flip Chip ◽

Packaging Technology ◽

Flip Chip Packaging

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Design of a capacitive pressure sensor based on flip-chip packaging technology

2010 11th International Conference on Electronic Packaging Technology & High Density Packaging ◽

10.1109/icept.2010.5582678 ◽

2010 ◽

Author(s):

Meng Nie ◽

Qing-An Huang ◽

Ming Qin ◽

Wei-Hua Li

Keyword(s):

Pressure Sensor ◽

Flip Chip ◽

Capacitive Pressure Sensor ◽

Packaging Technology ◽

Flip Chip Packaging

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Development of a 4-layer low cost flip chip packaging technology

53rd Electronic Components and Technology Conference, 2003. Proceedings. ◽

10.1109/ectc.2003.1216337 ◽

2004 ◽

Author(s):

A. Govind ◽

F. Ghahghahi

Keyword(s):

Flip Chip ◽

Low Cost ◽

Packaging Technology ◽

Flip Chip Packaging

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Cu pillars on substrates — a low cost alternative for the next generation of Flip Chip packaging technology

2010 Proceedings 60th Electronic Components and Technology Conference (ECTC) ◽

10.1109/ectc.2010.5490815 ◽

2010 ◽

Cited By ~ 1

Author(s):

D. Gupta ◽

H. Sato ◽

Y. Nakadaira

Keyword(s):

Flip Chip ◽

Low Cost ◽

Next Generation ◽

Packaging Technology ◽

Flip Chip Packaging

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Development of organic flip chip packaging technology for nanometer silicon incorporating copper metallization and low-k dielectric

2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE Cat. No.04CH37546) ◽

10.1109/ectc.2004.1319363 ◽

2004 ◽

Cited By ~ 1

Author(s):

A. Govind ◽

F. Ghahghahi

Keyword(s):

Flip Chip ◽

Copper Metallization ◽

Packaging Technology ◽

Flip Chip Packaging ◽

Low K

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A new flip chip packaging technology for the mid-range application space

52nd Electronic Components and Technology Conference 2002. (Cat. No.02CH37345) ◽

10.1109/ectc.2002.1008080 ◽

2003 ◽

Cited By ~ 3

Author(s):

R.D. Pendse ◽

Kyung-Moon Kim ◽

S. Tam

Keyword(s):

Flip Chip ◽

Packaging Technology ◽

Flip Chip Packaging

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Fabrication and Characteristics of Electroplated Sn-0.7Cu Micro-bumps for Flip-Chip Packaging

Korean Journal of Metals and Materials ◽

10.3365/kjmm.2011.49.5.411 ◽

2011 ◽

Vol 49 (6) ◽

Keyword(s):

Flip Chip ◽

Flip Chip Packaging

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Sensitivity analysis for geometrical parameters of BGA in flip chip packaging under random shear stress and thermal temperature

IEEE Transactions on Components Packaging and Manufacturing Technology ◽

10.1109/tcpmt.2021.3056218 ◽

2021 ◽

pp. 1-1

Author(s):

Liu Chu ◽

Peng Zhou ◽

Jiajia Shi ◽

Robin Braun

Keyword(s):

Sensitivity Analysis ◽

Shear Stress ◽

Flip Chip ◽

Geometrical Parameters ◽

Flip Chip Packaging

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A High-Linearity 76–85-GHz 16-Element 8-Transmit/8-Receive Phased-Array Chip With High Isolation and Flip-Chip Packaging

IEEE Transactions on Microwave Theory and Techniques ◽

10.1109/tmtt.2014.2341212 ◽

2014 ◽

Vol 62 (10) ◽

pp. 2337-2356 ◽

Cited By ~ 46

Author(s):

Bon-Hyun Ku ◽

Ozgur Inac ◽

Michael Chang ◽

Hyun-Ho Yang ◽

Gabriel M. Rebeiz

Keyword(s):

Flip Chip ◽

Phased Array ◽

High Isolation ◽

High Linearity ◽

Flip Chip Packaging

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Improved MEMS structure for stress-free flip-chip packaging

Journal of Micro/Nanolithography MEMS and MOEMS ◽

10.1117/1.3134087 ◽

2009 ◽

Vol 8 (2) ◽

pp. 021118 ◽

Cited By ~ 2

Author(s):

Toshitsugu Ueda

Keyword(s):

Flip Chip ◽

Flip Chip Packaging

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The Study of Underfill Epoxy Hardness in Reducing Curing Process Time for Flip Chip Packaging

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.462-463.1194 ◽

2011 ◽

Vol 462-463 ◽

pp. 1194-1199

Author(s):

Zainudin Kornain ◽

Azman Jalar ◽

Rozaidi Rashid ◽

Shahrum Abdullah

Keyword(s):

Thermal Expansion ◽

Flip Chip ◽

Ball Grid Array ◽

Process Time ◽

Curing Process ◽

Curing Time ◽

Hold Temperature ◽

Flip Chip Packaging ◽

Time Cycle ◽

The Impact

Underfilling is the vital process to reduce the impact of the thermal stress that results from the mismatch in the co-efficient of thermal expansion (CTE) between the silicon chip and the substrate in Flip Chip Packaging. This paper reported the pattern of underfill’s hardness during curing process for large die Ceramic Flip Chip Ball Grid Array (FC-CBGA). A commercial amine based underfill epoxy was dispensed into HiCTE FC-CBGA and cured in curing oven under a new method of two-step curing profile. Nano-identation test was employed to investigate the hardness of underfill epoxy during curing steps. The result has shown the almost similar hardness of fillet area and centre of the package after cured which presented uniformity of curing states. The total curing time/cycle in production was potentially reduced due to no significant different of hardness after 60 min and 120 min during the period of second hold temperature.

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