Wafer-Level Package using Pre-Applied Anisotropic Conductive Films (ACFs) for Flip-Chip Interconnections

2006 ◽  
Author(s):  
Ho-Young Son ◽  
Chang-Kyu Chung ◽  
Myung-Jin Yim ◽  
Kyung-Wook Paik
Keyword(s):  
Flip Chip ◽  
Wafer Level ◽  
Conductive Films ◽  
Wafer Level Package

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

scholarly journals Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)

2007 ◽  
Vol 30 (3) ◽  
pp. 221-227 ◽  
Author(s):  
Ho-Young Son ◽  
Chang-Kyu Chung ◽  
Myung-Jin Yim ◽  
Jin-Sang Hwang ◽  
Kyung-Wook Paik ◽  
...  
Keyword(s):  
Flip Chip ◽  
Wafer Level ◽  
Conductive Films

FOWLP Technology as an Wafer Level System in Packaging (SiP) Solution

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-41 ◽  
Author(s):  
Lewis(In Soo) Kang
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Low Cost ◽  
Industrial Applications ◽  
System Control ◽  
Wafer Level ◽  
Communication Module ◽  
3D Packaging ◽  
Control Application ◽  
Wafer Level Package

The market of Connectivity, Internet of Things (IoT), Wearable and Smart industrial applications leads Fan Out Wafer Level Package (FOWLP) technologies to a promising solution to overcome the limitation of conventional wafer level package, flip chip package and wire bonding package in terms of the solution of low cost, high performance and smaller form factor packaging. Moreover, FOWLP technology can be extended to system-in-package (SiP) area, such as multi chip 2D package and 3D stack package types. nepes Corporation has developed several advanced package platforms such as single, multi dies and 2D, 3D packaging by using FOWLP and embedding technologies. To fulfill SiP (system-in-package) with FOWLP, several dies and components have been embedded into one package which offers 40~90 % of volumetric shrink compared to the current module system with the flexibility of product design for end users. 3D package technology of PoP (Package on Package) structure will be introduced for communication module and system control application.

Flexible Chip-on-Flex (COF) and embedded Chip-in-Flex (CIF) packages by applying wafer level package (WLP) technology using anisotropic conductive films (ACFs)

2012 ◽  
Vol 52 (1) ◽  
pp. 225-234 ◽  
Author(s):  
Kyoung-Lim Suk ◽  
Ho-Young Son ◽  
Chang-Kyu Chung ◽  
Joong Do Kim ◽  
Jin-Woo Lee ◽  
...  
Keyword(s):  
Wafer Level ◽  
Conductive Films ◽  
Wafer Level Package ◽  
Embedded Chip
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