scholarly journals Wafer-Level Flip Chip Packages Using Preapplied Anisotropic Conductive Films (ACFs)

2007 ◽  
Vol 30 (3) ◽  
pp. 221-227 ◽  
Author(s):  
Ho-Young Son ◽  
Chang-Kyu Chung ◽  
Myung-Jin Yim ◽  
Jin-Sang Hwang ◽  
Kyung-Wook Paik ◽  
...  
Keyword(s):  
Flip Chip ◽  
Wafer Level ◽  
Conductive Films

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages (WLCSP)

2011 ◽  
Author(s):  
Pushkraj Tumne ◽  
Vikram Venkatadri ◽  
Santosh Kudtarkar ◽  
Michael Delaus ◽  
Daryl Santos ◽  
...  
Keyword(s):  
Flip Chip ◽  
Bulk Solder ◽  
Consumer Electronics ◽  
Drop Test ◽  
Design Parameters ◽  
Mechanical Shock ◽  
Wafer Level ◽  
Cross Sectional ◽  
Right Censored Data ◽  
Solder Balls

Today’s consumer market demands electronics that are smaller, faster and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer Level Chip Scale Package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence the emphasis of reliability is shifting towards study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the PCB by solder balls. The size of these solder balls is typically large enough (300μm pre-reflow for 0.5mm pitch and 250μm pre-reflow for 0.4mm pitch) to avoid use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different Silver (Ag) content, backside lamination with different thickness, WLCSP type –Direct and Re-Distribution Layer (RDL), bond pad thickness, and sputtered versus electroplated Under Bump Metallurgy (UBM) deposition methods for 8×8, 9×9, and 10×10 array sizes. The test vehicles built using these design parameters were drop tested using JEDEC recommended test boards and conditions as per JESD22-B11. Cross sectional analysis was used to identify, confirm, and classify the intermetallic, and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data was collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and un-grouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Active and Passive Devices Embedded in Laminate-Based Multilayer Board

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001253-001283
Author(s):  
Satoshi Okude ◽  
Kazushisa Itoi ◽  
Masahiro Okamoto ◽  
Nobuki Ueta ◽  
Osamu Nakao
Keyword(s):  
High Temperature ◽  
Thermal Cycling ◽  
Flip Chip ◽  
Wafer Level ◽  
Active Device ◽  
Electrical Connection ◽  
Passive Devices ◽  
High Temperature Storage ◽  
Circuit Resistance ◽  
Temperature Storage

We have developed active and passive devices embedded multilayer board utilizing our laminate-based WLCSP embedding technology. The proposed embedded board is realized by laminating plural circuit formed polyimide films together by adhesive with thin devices being arranged in between those polyimide layers. The electrical connection via has a filled via structure composed of the alloy forming conductive paste which ensures high reliable connection. The embedded active device is WLCSP which has no solder bump on its pads therefore the thickness of the die is reduced to 80 microns. The embedded passive device is a chip resistor or capacitor whose thickness is 150 microns with copper electrodes. The electrical connection between components and board's circuits are made by same conductive paste vias. The thin film based structure and low profile devices yields the 260 microns thickness board which is the thinnest embedded of its kind in the world. To confirm the reliability of the embedded board, we have performed several reliability tests on the WLCSP and resistors embedded TEG board of 4 polyimide/5 copper circuit layers. As environmental tests, we performed a moisture reflow test compliant to JEDEC MSL2 followed by a thermal cycling test (−55 deg.C to 125 deg.C, 1000cycles) and a high temperature storage test (150 deg.C). All tested samples passed the moisture reflow test and showed no significant change of circuit resistance after the thermal cycling/high temperature storage tests. Moreover, mechanical durability of the board was also confirmed by bending the devices embedded portion. The embedded device was never broken and the circuit resistance change was also within acceptable range. The proposed embedded board will open up a new field of device packaging. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-3-12.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Fan-in WLP: Technology and Market Trends

2015 ◽  
Vol 2015 (1) ◽  
pp. 000067-000072 ◽  
Author(s):  
A. Ivankovic ◽  
T. Buisson ◽  
S. Kumar ◽  
A. Pizzagalli ◽  
J. Azemar ◽  
...  
Keyword(s):  
Flip Chip ◽  
Semiconductor Industry ◽  
Cost Benefit ◽  
Current Status ◽  
Wafer Level ◽  
New Era ◽  
Device Scaling ◽  
Depth Analysis ◽  
Application Diversification ◽  
The Cost

The semiconductor industry is facing a new era in which device scaling and cost reduction will not continue on the path they followed for the past few decades, with Moore's law in its foundation. Advanced nodes do not bring the desired cost benefit anymore and R&D expenses for new lithography solutions and devices in sub-10nm nodes are rising substantially. Subsequently, new market shifts are expected in due time, with “Internet of Things” (IoT) getting ready to take over pole market driver position from mobile. In these circumstances, where front-end-of-line (FEOL) scaling options remain uncertain and IoT promises application diversification, in order to answer market demands, the industry seeks further performance and functionality boosts in package level integration. Emerging packages such as fan-out wafer level packages, 2.5D/3D IC and related System-in-Package (SiP) solutions together with more conventional but upgraded flip chip BGAs aim to bridge the gap and revive the cost/performance curve. In such an environment, what is the importance of fan-in wafer level packages (FI WLP), the current status of the fan-in WLP industry and how will fan-in WLP market and technology evolve? This work aims to answer these questions by performing an in-depth analysis on fan-in WLP market dynamics and technology trends.

Creating Semiconductor Value through Advanced Package Technology

2016 ◽  
Vol 2016 (S1) ◽  
pp. S1-S46
Author(s):  
Ron Huemoeller
Keyword(s):  
Big Five ◽  
Flip Chip ◽  
Microelectromechanical Systems ◽  
Technology Innovation ◽  
Low Cost ◽  
Semiconductor Industry ◽  
Significant Shift ◽  
Wafer Level ◽  
Chip Scale Package ◽  
Advanced Packaging

Over the past few years, there has been a significant shift from PCs and notebooks to smartphones and tablets as drivers of advanced packaging innovation. In fact, the overall packaging industry is doing quite well today as a result, with solid growth expected to create a market value in excess of $30B USD by 2020. This is largely due to the technology innovation in the semiconductor industry continuing to march forward at an incredible pace, with silicon advancements in new node technologies continuing on one end of the spectrum and innovative packaging solutions coming forward on the other in a complementary fashion. The pace of innovation has quickened as has the investments required to bring such technologies to production. At the packaging level, the investments required to support the advancements in silicon miniaturization and heterogeneous integration have now reached well beyond $500M USD per year. Why has the investment to support technology innovation in the packaging community grown so much? One needs to look no further than the complexity of the most advanced package technologies being used today and coming into production over the next year. Advanced packaging technologies have increased in complexity over the years, transitioning from single to multi-die packaging, enabled by 3-dimensional integration, system-in-package (SiP), wafer-level packaging (WLP), 2.5D/3D technologies and creative approached to embedding die. These new innovative packaging technologies enable more functionality and offer higher levels of integration within the same package footprint, or even more so, in an intensely reduced footprint. In an industry segment that has grown accustomed to a multitude of package options, technology consolidation seems evident, producing “The Big Five” advanced packaging platforms. These include low-cost flip chip, wafer-level chip-scale package (WLCSP), microelectromechanical systems (MEMS), laminate-based advanced system-in-package (SiP) and wafer-based advanced SiP designs. This presentation will address ‘The Big Five’ packaging platforms and how they are adding value to the Semiconductor Industry.

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