Thermal Enhancement of Systems using Organic Flip-Chip Packages (FC-PBGA) with an Alternate Cooling Path through the Printed Wiring Board

2006 ◽  
Author(s):  
V. Calmidi ◽  
I. Memis
Keyword(s):  
Flip Chip ◽  
Printed Wiring Board ◽  
Cooling Path ◽  
Thermal Enhancement ◽  
Wiring Board

Effective Thermal Conductivity of Six Sigma’s Copper Reinforced Column Grid Array Interconnect for Ceramic Microelectronic Packages

2010 ◽  
Author(s):  
Mark Eblen
Keyword(s):  
Thermal Conductivity ◽  
Integrated Circuits ◽  
Effective Thermal Conductivity ◽  
Flip Chip ◽  
Heat Removal ◽  
Thermal Design ◽  
Printed Wiring Board ◽  
Wiring Board ◽  
High Lead

Thermal management of flip chip style integrated circuits often relies on thermal conduction through the ceramic package and high lead solder grid array leads into the printed wiring board as the primary path for heat removal. Thermal analysis of this package configuration requires accurate characterization of the sometimes geometrically complex package-to-board interface. Given the unique structure of the Six Sigma column grid array (CGA) interconnect, a detailed finite element submodel was used to numerically derive the effective thermal conductivity with comparisons to a conventional CGA interconnect. Once an effective thermal conductivity value is obtained, the entire interconnect layer can be represented as a fictitious cuboid layer for inclusion in a more traditional “closed-form” thermal resistance calculation. This method allows the package designer a quick and robust method to evaluate initial thermal design study tradeoffs.

Manufacturing Substrates with Embedded Passives

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002011-002050
Author(s):  
Rabindra N. Das ◽  
Konstantinos I. Papathomas ◽  
John M. Lauffer ◽  
Mark D. Poliks ◽  
Voya R. Markovich
Keyword(s):  
High Performance ◽  
Flip Chip ◽  
Electrical Characterization ◽  
Printed Wiring Board ◽  
Digital Products ◽  
Capacitance Density ◽  
Embedded Passives ◽  
Wiring Board ◽  
Electronic Assemblies

Passives account for a very large part of today's electronic assemblies. This is particularly true for digital products such as cellular phones, camcorders, computers and several critical defense devices. This paper presents an entire process from design and fabrication to electrical characterization and reliability test of embedded passives on organic multilayered substrates. A variety of thin film capacitor and resistors were utilized to manufacture high-performance embedded passives. The electrical properties of capacitors fabricated from polymer-ceramic nanocomposites showed a stable capacitance and low loss over a wide temperature range. We have designed and fabricated several printed wiring board (PWB) and flip-chip package test vehicles focusing on resistors and capacitors. Two basic capacitor cores were used for this study. One is a layer capacitor. The second capacitor in this case study was discrete capacitor. In both cases, capacitance values are defined by the feature size, thickness and dielectric constant of the polymer-ceramic compositions. Nanocomposite can be directly deposited either by liquid coating or screen printing. Alternatively, nanocomposite thin films can be laminated and capacitor laminate can be used as the base substrate for subsequent build-up processing. For example, Resin Coated Copper Capacitive (RC3) nanocomposites were used to fabricate 35 mm substrates with a two by two array of 15mm square isolated epoxy based regions; each having two to six RC3 based embedded capacitance layers. The capacitor fabrication is based on a sequential build-up technology employing a first patternable electrode. After patterning of the electrode, RC3 nanocomposite can be laminated within PCB. Embedded passive cores are showing high capacitance density ranging from 15 nF to 30nF depending on Cu area, composition and thickness of the capacitors. Reliability of the capacitors was ascertained by IR-reflow, thermal cycling, PCT (Pressure Cooker Test ) and solder shock. Embedded capacitors were stable after PCT and solder shock. Capacitance change was less than 5% after IR reflow (assembly) preconditioning (3X, 245 °C) and 1000 cycles DTC (Deep Thermal Cycle).

Three-Dimensional Versus Two-Dimensional Finite Element Modeling of Flip-Chip Packages

1999 ◽  
Vol 121 (3) ◽  
pp. 196-201 ◽  
Author(s):  
Q. Yao ◽  
J. Qu
Keyword(s):  
Finite Element ◽  
Flip Chip ◽  
Three Dimensional ◽  
Two Dimensional ◽  
Mechanical Interaction ◽  
Printed Wiring Board ◽  
Dimensional Finite Element ◽  
Dimensional Models ◽  
Flip Chip Assembly ◽  
Wiring Board

In this study, both two-dimensional and three-dimensional finite element analyses were used to study the stress distribution in and deflection of the flip chip assembly under thermal loading. It is found that the three-dimensional results compared favorably with experimental measurements, while the two-dimensional results consistently overestimate both stresses and deflection. Among the two-dimensional models, the plane stress assumption seems to yield results closer to the full three-dimensional predictions. Furthermore, three-dimensional models were used to investigate the effect of printed wiring board size on the overall deflection of the flip-chip assembly. This size effect of the printed wiring board has significant implications on the design of multi-chip modules. The results indicate that a square array placement pattern is preferable to a staggered array for multiple chip modules in order to reduce mechanical interaction between chips. For square arrays, such mechanical interaction between chips can be neglected when the minimum distance between adjacent chips is more than 2 times the chip size.

A Novel Projection Moiré System for Measuring PWBA Warpage Using Simulated Optimized Convective Reflow Process

2009 ◽  
Vol 131 (2) ◽  
Author(s):  
Reinhard E. Powell ◽  
I. Charles Ume
Keyword(s):  
Measurement System ◽  
Flip Chip ◽  
Active Contours ◽  
Printed Wiring Board ◽  
Reflow Process ◽  
Shadow Moire ◽  
Shadow Moiré ◽  
Plastic Ball ◽  
Wiring Board ◽  
Projection Moire

The shadow moiré technique is a widely used method of measuring printed wiring board (PWB) warpage. It has a high resolution, high accuracy, and is suitable for use in an online environment. The shortcoming of the shadow moiré technique is that it cannot be used to measure PWBs populated with chip packages. In this paper, a novel warpage measurement system based on the projection moiré technique is presented. The system can be used to measure bare PWBs, as well as PWBs populated with chip packages. In order to use the projection moiré system to accurately determine the warpage of PWBs and chip packages separately, an automated chip package detection algorithm based on active contours is utilized. Unlike the shadow moiré technique, which uses a glass grating, the projection moiré technique uses a virtual grating. The virtual grating sizes can be adjusted, making it versatile for measuring various PWB and chip package sizes. Without the glass grating, which is a substantial heat inertia, the PWB/printed wiring board assembly (PWBA) sample can be heated more evenly during the thermal process. The projection moiré system described in this paper can also be used to measure the warpage of PWBs/PWBAs/chip packages during convective reflow processes. In this paper, the characteristics of the projection moiré warpage measurement system will be described. In addition, the system will be used to measure the warpage of a PWB and plastic ball grid array packages during a Lee optimized convective reflow process (Lee, N.-C., 2002, Reflow Soldering Processes and Troubleshooting SMT, BGA, CSP, and Flip Chip Technologies, Butterworth-Heinemann, MA). It is concluded that this projection moiré warpage measurement system is a powerful tool to study the warpage of populated PWBs during convective reflow processes.

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