scholarly journals Predictive failure model of flip chip on board component level assemblies

2004 ◽  
Author(s):  
J. Muncy ◽  
T. Lazarakis ◽  
D. Baldwin
Keyword(s):  
Flip Chip ◽  
Failure Model ◽  
Component Level ◽  
Predictive Failure

Experimental definition of a failure model for the tribological behaviour of polytetrafluoroethylene bronze compounds

2009 ◽  
Vol 223 (5) ◽  
pp. 807-815 ◽  
Author(s):  
I Gódor ◽  
Z Major ◽  
Sz Vezér ◽  
F Grün
Keyword(s):  
Test System ◽  
Failure Model ◽  
Micro Structure ◽  
Tribological Behaviour ◽  
Component Level ◽  
High Chemical ◽  
Similar Composition ◽  
Definition Of ◽  
Microscopy Techniques ◽  
Laboratory Specimen

Because of their high chemical and thermal resistance and advantageous friction behaviour, polytetrafluoroethylene (PTFE) compounds are frequently used in various engineering applications, especially for pressurized seals. To adjudge the applicability, and to establish a reliable ranking of various compounds with similar composition and micro-structure for tribological systems, a number of bronze-particle-filled PTFE materials (PTFE-Bz compounds) were investigated with a seal test system at the component level. The two best performing materials in these component tests, termed PTFE-Bz9 and PTFE-Bz14 in this article, were then selected for further, more detailed thermo-mechanical and tribological investigations on a laboratory specimen level. Furthermore, extensive failure analysis of both the worn seals and the test specimens were carried out using laser confocal and scanning electron microscopy techniques. Finally, based on the experimental results a model for describing the functionality and of the failure behaviour of these materials was developed and described.

Package Technology Selection of 28nm High Power FPGA with Pb-Free Solder Bumps: Flip Chip Molded BGA (FCMBGA) versus Traditional Flip Chip Bare Die Package

2013 ◽  
Vol 2013 (1) ◽  
pp. 000239-000244
Author(s):  
Michael Lyakas ◽  
Corey Reichman ◽  
Miguel Jimarez ◽  
Romina Mimi Ocampo ◽  
Aaron Elberg ◽  
...  
Keyword(s):  
High Power ◽  
Flip Chip ◽  
Mechanical Damage ◽  
Temperature Cycling ◽  
Technology Selection ◽  
Design Rule ◽  
Resistance Testing ◽  
Temperature Cycle ◽  
Reliability Testing ◽  
Component Level

Selecting the optimal flip-chip package technology for the next generation 28nm FPGA is critical not only to meet reliability benchmarks for Pb-free bumps, but also in meeting the field-use environment requirements for high power devices. Component level reliability testing was conducted on three separate package types: Bare die flip chip BGA (FCBGA), flip chip molded BGA with capillary underfill (FCMBGA w/CUF), and flip chip molded BGA with molded underfill. (FCMBGA). Testing was conducted independently at two separate sites. Testing included moisture resistance testing (MRT), temperature cycle (JESD22-A104 Condition Level B), and a hybrid test combining 100 hours of unbiased HAST (JESD22-A118A) with temperature cycling. Reliability monitoring was conducted through multiple means including electrical testing for circuit continuity, CSAM imaging at frequent read points to monitor silicon integrity and underfill adhesion performance, cross-sections for the inspection of bump crack propagation, and FIB analysis of the UBM structure after test completion. In addition to reliability testing of three flip chip BGA platforms, other usage factors were considered. These include package specific design rule flexibility for passive placement and future generation packaging requirements. The results of the evaluation demonstrated that bump integrity remained strong for all three package types – showing no cracks after 1,500 temperature cycles, hybrid testing, or MRT. Ultimately, the FCMBGA with molded underfill was selected based on the quality of the bumps after testing, the design rule flexibility for capacitor placement, and improved component protection from mechanical damage.

Copper Migration in Flip-Chip Substrates Under Biased-HAST Conditions

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002465-002480
Author(s):  
Matthew E. Stahley ◽  
John W. Osenbach
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Stress Test ◽  
Failure Mechanisms ◽  
Failure Model ◽  
Corrosion Failure ◽  
Long Duration ◽  
Aluminum Corrosion ◽  
Accelerated Stress Test

Biased-humidity testing is a critical reliability qualification requirement for integrated circuit packages. The benchmark of THB (Temperature Humidity Bias) at 85C/85%RH/bias for 1000 hours is a long duration test, so biased-HAST (biased Highly Accelerated Stress Test) conditions are adopted. Accelerated biased-HAST durations are based on aluminum corrosion failure mechanisms and may not be applicable to other materials such as in flip-chip packages. One such failure mechanism is discussed here. Flip-chip packages with build-up substrates were exposed to biased-humidity at 85C, 110C, or 130C and 85%RH. After 96 hours of 130C/85%RH/bias, failures occurred with signatures ranging from bake-recoverable leakage to shorts. Physical failure analysis revealed copper migration in the substrate build-up dielectric rather than classical CAF (Conductive Anodic Filament) within the substrate core. No copper migration occurred with conditions of 110C/85%RH/bias, 85C/85%RH/bias, or 130C/85%RH/no-bias. Given that the JEDEC biased humidity durations are 96 hours at 130C/85%RH, 264 hours at 110C/85%RH, or 1000 hours at 85C/85%RH, it is concluded that the JEDEC acceleration function is not applicable for this failure mechanism. A failure model is proposed based on humidity induced reduction of the glass transition temperature (Tg) of the build-up dielectric. Bond strength decreases and free volume increases above Tg, and the combination results in the formation of localized channels in the build-up dielectric where electrochemical migration of copper occurs under bias and humidity. Copper migration does not occur for conditions of humidity/bias below Tg, humidity/no-bias above Tg, and no humidity/bias near Tg. This indicates there is likely a threshold in humidity and/or temperature, below which copper migration does not occur. These results further demonstrate that caution must be used when employing accelerated reliability tests, as they may introduce failure mechanisms that would not occur in the field.

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