Copper Migration in Flip-Chip Substrates Under Biased-HAST Conditions

2011 ◽  
Vol 2011 (DPC) ◽  
pp. 002465-002480
Author(s):  
Matthew E. Stahley ◽  
John W. Osenbach
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Stress Test ◽  
Failure Mechanisms ◽  
Failure Model ◽  
Corrosion Failure ◽  
Long Duration ◽  
Aluminum Corrosion ◽  
Accelerated Stress Test

Biased-humidity testing is a critical reliability qualification requirement for integrated circuit packages. The benchmark of THB (Temperature Humidity Bias) at 85C/85%RH/bias for 1000 hours is a long duration test, so biased-HAST (biased Highly Accelerated Stress Test) conditions are adopted. Accelerated biased-HAST durations are based on aluminum corrosion failure mechanisms and may not be applicable to other materials such as in flip-chip packages. One such failure mechanism is discussed here. Flip-chip packages with build-up substrates were exposed to biased-humidity at 85C, 110C, or 130C and 85%RH. After 96 hours of 130C/85%RH/bias, failures occurred with signatures ranging from bake-recoverable leakage to shorts. Physical failure analysis revealed copper migration in the substrate build-up dielectric rather than classical CAF (Conductive Anodic Filament) within the substrate core. No copper migration occurred with conditions of 110C/85%RH/bias, 85C/85%RH/bias, or 130C/85%RH/no-bias. Given that the JEDEC biased humidity durations are 96 hours at 130C/85%RH, 264 hours at 110C/85%RH, or 1000 hours at 85C/85%RH, it is concluded that the JEDEC acceleration function is not applicable for this failure mechanism. A failure model is proposed based on humidity induced reduction of the glass transition temperature (Tg) of the build-up dielectric. Bond strength decreases and free volume increases above Tg, and the combination results in the formation of localized channels in the build-up dielectric where electrochemical migration of copper occurs under bias and humidity. Copper migration does not occur for conditions of humidity/bias below Tg, humidity/no-bias above Tg, and no humidity/bias near Tg. This indicates there is likely a threshold in humidity and/or temperature, below which copper migration does not occur. These results further demonstrate that caution must be used when employing accelerated reliability tests, as they may introduce failure mechanisms that would not occur in the field.

Investigation of High Frequency Failures on a 0.35μm CMOS IC

1999 ◽  
Author(s):  
Alan Kennen ◽  
John F. Guravage ◽  
Lauren Foster ◽  
John Kornblum
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Ion Beam ◽  
Stress Test ◽  
Design For Test ◽  
Interface Failure ◽  
Serial Interface ◽  
High Impedance

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

Discussion on the Interference Phenomenon of Multiple Failure Mechanisms and Determination of Dominant Failure Mechanism for Pressure Equipments

2016 ◽  
Author(s):  
Chen Xuedong ◽  
Ai Zhibin ◽  
Li Rongrong ◽  
Fan Zhichao ◽  
Xu Shuangqing ◽  
...  
Keyword(s):  
Stainless Steel ◽  
Austenitic Stainless Steel ◽  
Failure Mechanism ◽  
Failure Mechanisms ◽  
Pressure Vessels ◽  
Intergranular Stress Corrosion ◽  
Interference Phenomenon ◽  
Corrosion Failure ◽  
Media Environment

For petrochemical pressure vessels subjected to complex media environment, the competition, inhibition, promotion and interference of multiple failure mechanisms have been discussed by several failure case analyses and experimental investigation. The main factors that influence formation of dominant failure mechanism are analyzed and the judgment principles of the dominant failure mechanism are raised in the case of interaction of multiple failure mechanisms. In this paper, relevant mechanisms are also discussed, e.g. intergranular corrosion and intergranular stress corrosion failure mechanisms of austenitic stainless steel, failure mechanisms of austenitic stainless steel when Cl− and alkaline environment exist concurrently and failure mechanism of austenitic stainless steel when medium such as Cl−, CO2, H2S, H2O, etc. exist concurrently.

On the role of tin underlays for the prevention of thermal grooving in thin gold films

1986 ◽  
Vol 44 ◽  
pp. 732-733
Author(s):  
Jin Young Kim ◽  
R. E. Hummel ◽  
R. T. DeHoff
Keyword(s):  
Thin Film ◽  
Free Surface ◽  
Grain Boundary ◽  
Beneficial Effect ◽  
Failure Mechanism ◽  
Failure Mechanisms ◽  
Distinct Advantage ◽  
Gold Films ◽  
Gold Thin Film

Gold thin film metallizations in microelectronic circuits have a distinct advantage over those consisting of aluminum because they are less susceptible to electromigration. When electromigration is no longer the principal failure mechanism, other failure mechanisms caused by d.c. stressing might become important. In gold thin-film metallizations, grain boundary grooving is the principal failure mechanism.Previous studies have shown that grain boundary grooving in gold films can be prevented by an indium underlay between the substrate and gold. The beneficial effect of the In/Au composite film is mainly due to roughening of the surface of the gold films, redistribution of indium on the gold films and formation of In2O3 on the free surface and along the grain boundaries of the gold films during air annealing.

Application of Lock-in Thermography on PCB for Fault Localization and Validation of Failure Mechanism Due to External Discrete Component Variation

2010 ◽  
Author(s):  
William Ng ◽  
Kevin Weaver ◽  
Zachary Gemmill ◽  
Herve Deslandes ◽  
Rudolf Schlangen
Keyword(s):  
Failure Mechanism ◽  
Integrated Circuit ◽  
Printed Circuit Board ◽  
Hot Spot ◽  
Circuit Board ◽  
Discrete Component ◽  
Printed Circuit ◽  
Thermal Signature ◽  
Lock In

Abstract This paper demonstrates the use of a real time lock-in thermography (LIT) system to non-destructively characterize thermal events prior to the failing of an integrated circuit (IC) device. A case study using a packaged IC mounted on printed circuit board (PCB) is presented. The result validated the failing model by observing the thermal signature on the package. Subsequent analysis from the backside of the IC identified a hot spot in internal circuitry sensitive to varying value of external discrete component (inductor) on PCB.

In-Line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results

2000 ◽  
Author(s):  
Julie Segal ◽  
Arman Sagatelian ◽  
Bob Hodgkins ◽  
Tom Ho ◽  
Ben Chu ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Integrated Circuit ◽  
Failure Mechanisms ◽  
Memory Devices ◽  
Line Defect ◽  
Yield Improvement ◽  
Electrical Test ◽  
Large Numbers ◽  
Improvement Process ◽  
Existing Data

Abstract Physical failure analysis (FA) of integrated circuit devices that fail electrical test is an important part of the yield improvement process. This article describes how the analysis of existing data from arrayed devices can be used to replace physical FA of some electrical test failures, and increase the value of physical FA results. The discussion is limited to pre-repair results. The key is to use classified bitmaps and determine which signature classification correlates to which type of in-line defect. Using this technique, physical failure mechanisms can be determined for large numbers of failures on a scale that would be unfeasible with de-processing and physical FA. If the bitmaps are classified, two-way correlation can be performed: in-line defect to bitmap failure, as well as bitmap signature to in-line defect. Results also demonstrate the value of analyzing memory devices failures, even those that can be repaired, to gain understanding of defect mechanisms.

Infra-Red Reflectance Microscopy (IRRM) for Daisy Chain Flip Chip Device Failure Analysis

2004 ◽  
Author(s):  
Carlo Grilletto ◽  
Steve Hsiung ◽  
Andrew Komrowski ◽  
John Soopikian ◽  
Daniel J.D. Sullivan ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
State Of The Art ◽  
Failure Mechanisms ◽  
Simple Metal ◽  
X Ray ◽  
Infra Red ◽  
Cause Of Failure ◽  
Reflectance Microscopy ◽  
Ir Emission

Abstract This paper describes a method to "non-destructively" inspect the bump side of an assembled flip-chip test die. The method is used in conjunction with a simple metal-connecting "modified daisy chain" die and makes use of the fact that polished silicon is transparent to infra-red (IR) light. The paper describes the technique, scope of detection and examples of failure mechanisms successfully identified. It includes an example of a shorting anomaly that was not detectable with the state of the art X-ray equipment, but was detected by an IR emission microscope. The anomalies, in many cases, have shown to be the cause of failure. Once this has been accomplished, then a reasonable deprocessing plan can be instituted to proceed with the failure analysis.

scholarly journals FCCSP IMC growth under reliability stress follows automotive criteria

2019 ◽  
Vol 3 (1) ◽  
pp. 70-83
Author(s):  
Wei Wei Liu ◽  
Berdy Weng ◽  
Scott Chen
Keyword(s):  
High Temperature ◽  
Flip Chip ◽  
Stress Test ◽  
Temperature Cycling ◽  
Content Type ◽  
Initial Stage ◽  
High Temperature Storage ◽  
Temperature Cycling Test ◽  
Temperature Storage

Purpose The Kirkendall void had been a well-known issue for long-term reliability of semiconductor interconnects; while even the KVs exist at the interfaces of Cu and Sn, it may still be able to pass the condition of unbias long-term reliability testing, especially for 2,000 cycles of temperature cycling test and 2,000 h of high temperature storage. A large number of KVs were observed after 200 cycles of temperature cycling test at the intermetallic Cu3Sn layer which locate between the intermetallic Cu6Sn5 and Cu layers. These kinds of voids will grow proportional with the aging time at the initial stage. This paper aims to compare various IMC thickness as a function of stress test, the Cu3Sn and Cu6Sn5 do affected seriously by heat, but Ni3Sn4 is not affected by heat or moisture. Design/methodology/approach The package is the design in the flip chip-chip scale package with bumping process and assembly. The package was put in reliability stress test that followed AEC-Q100 automotive criteria and recorded the IMC growing morphology. Findings The Cu6Sn5 intermetallic compound is the most sensitive to continuous heat which grows from 3 to 10 µm at high temperature storage 2,000 h testing, and the second is Cu3Sn IMC. Cu6Sn5 IMC will convert to Cu3Sn IMC at initial stage, and then Kirkendall void will be found at the interface of Cu and Cu3Sn IMC, which has quality concerning issue if the void’s density grows up. The first phase to form and grow into observable thickness for Ni and lead-free interface is Ni3Sn4 IMC, and the thickness has little relationship to the environmental stress, as no IMC thickness variation between TCT, uHAST and HTSL stress test. The more the Sn exists, the thicker Ni3Sn4 IMC will be derived from this experimental finding compare the Cu/Ni/SnAg cell and Ni/SnAg cell. Research limitations/implications The research found that FCCSP can pass automotive criteria that follow AEC-Q100, which give the confidence for upgrading the package type with higher efficiency and complexities of the pin design. Practical implications This result will impact to the future automotive package, how to choose the best package methodology and what is the way to do the package. The authors can understand the tolerance for the kind of flip chip package, and the bump structure is then applied for high-end technology. Originality/value The overall three kinds of bump structures, Cu/Ni/SnAg, Cu/SnAg and Ni/SnAg, were taken into consideration, and the IMC growing morphology had been recorded. Also, the IMC had changed during the environmental stress, and KV formation was reserved.

scholarly journals Fabrication and Packaging of CMUT Using Low Temperature Co-Fired Ceramic

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 553 ◽  
Author(s):  
Fikret Yildiz ◽  
Tadao Matsunaga ◽  
Yoichi Haga
Keyword(s):  
Low Temperature ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Ultrasonic Transducer ◽  
Silicon On Insulator ◽  
Anodic Bonding ◽  
Lateral Side ◽  
Membrane Thickness ◽  
Bonding Performance ◽  
Complex Admittance

This paper presents fabrication and packaging of a capacitive micromachined ultrasonic transducer (CMUT) using anodically bondable low temperature co-fired ceramic (LTCC). Anodic bonding of LTCC with Au vias-silicon on insulator (SOI) has been used to fabricate CMUTs with different membrane radii, 24 µm, 25 µm, 36 µm, 40 µm and 60 µm. Bottom electrodes were directly patterned on remained vias after wet etching of LTCC vias. CMUT cavities and Au bumps were micromachined on the Si part of the SOI wafer. This high conductive Si was also used as top electrode. Electrical connections between the top and bottom of the CMUT were achieved by Au-Au bonding of wet etched LTCC vias and bumps during anodic bonding. Three key parameters, infrared images, complex admittance plots, and static membrane displacement, were used to evaluate bonding success. CMUTs with a membrane thickness of 2.6 µm were fabricated for experimental analyses. A novel CMUT-IC packaging process has been described following the fabrication process. This process enables indirect packaging of the CMUT and integrated circuit (IC) using a lateral side via of LTCC. Lateral side vias were obtained by micromachining of fabricated CMUTs and used to drive CMUTs elements. Connection electrodes are patterned on LTCC side via and a catheter was assembled at the backside of the CMUT. The IC was mounted on the bonding pad on the catheter by a flip-chip bonding process. Bonding performance was evaluated by measurement of bond resistance between pads on the IC and catheter. This study demonstrates that the LTCC and LTCC side vias scheme can be a potential approach for high density CMUT array fabrication and indirect integration of CMUT-IC for miniature size packaging, which eliminates problems related with direct integration.

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