Recent advances on a wafer-level flip chip packaging process

2002 ◽  
Author(s):  
Q. Tong ◽  
B. Ma ◽  
E. Zhan ◽  
A. Savoca ◽  
L. Nguyen ◽  
...  
Keyword(s):  
Flip Chip ◽  
Wafer Level ◽  
Packaging Process ◽  
Recent Advances ◽  
Flip Chip Packaging

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

Recent advances in modeling the underfill process in flip-chip packaging

2007 ◽  
Vol 38 (1) ◽  
pp. 67-75 ◽  
Author(s):  
J.W. Wan ◽  
W.J. Zhang ◽  
D.J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Recent Advances ◽  
Flip Chip Packaging

Flip Chip Packaging of Wafer Level Encapsulated RF MEMS Tunable Capacitors

2013 ◽  
Author(s):  
Shawn J. Cunningham ◽  
Yvonne Heng ◽  
Nabeel Idrisi ◽  
Brad Nelson ◽  
John McKillop
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Rf Mems ◽  
Temperature Cycling ◽  
Battery Life ◽  
Mems Devices ◽  
Wafer Level ◽  
Element Analysis ◽  
Tunable Capacitors ◽  
Flip Chip Packaging

Wireless handheld communications has identified significant benefits of tuning that include fewer dropped calls, increased battery life and improved user experience. The tuning can be part of the antenna, power amplifier (PA), filtering, or part of a fully integrated radio front end (FE). RF MEMS tunable capacitors have been integrated with 0.18 μm RF HVCMOS to address the need for tuning in wireless communications. These integrated, MEMS tunable capacitors are hermetically encapsulated at the wafer level, but the integrity of the encapsulation must be maintained during BEOL operations. The BEOL operations include shipping and handling, passivation coat and cure, solder bumping (screen printed or electroplated), backside grinding (BSG), dicing, and pick and place. In this paper we will describe, the flip chip packaging of the wafer level encapsulated MEMS devices including finite element analysis. The flip chip packaging of ASIC die is primarily concerned with solder bump reliability during such qualification stresses as temperature cycling and drop testing. The flip chip packaging of a wafer level encapsulated MEMS device has additional concerns that include encapsulation integrity and device package sensitivity. The die thickness, underfill, and encapsulation dimension have been varied to minimize the deflection and stress associated with the encapsulation. The primary failure mode associated with the overstress of the encapsulation is a cracked lid that will lead to the ingress of moisture and a rise in the cavity pressure from to atmospheric conditions. The failure can be detected by an increase in the MEMS switching time and frequency response or by a return to zero failure (RTZ) associated with device stiction. A low modulus and low CTE UF has been implemented for the lowest deflection and stress. The lowest deflection and stress is provided by eliminating the UF, but this is not feasible for the purpose of solder bump reliability. In practice, the MEMS encapsulation is robust to the printed solder bumping process that includes placement and removal of the bump screen and the squeegee of solder past into the solder screen. The MEMS encapsulation is robust to the attachment and removal of BSG tape and the pressures associated with BSG. The final dicing operation has not demonstrated any detrimental impact on the MEMS encapsulation. The final demonstration of success is the assembly of the MEMS tunable capacitor die to a laminate substrate using lead-free solder and underfill.

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