Flip chip package design optimization

2003 ◽  
Author(s):  
J.N. Shenoy ◽  
S. Dandia
Keyword(s):  
Design Optimization ◽  
Flip Chip ◽  
Package Design

Application of an Epoxy Cap in a Flip-Chip Package Design

1989 ◽  
Vol 111 (1) ◽  
pp. 16-20 ◽  
Author(s):  
E. Suhir
Keyword(s):  
Thermal Expansion ◽  
Flip Chip ◽  
Coefficient Of Thermal Expansion ◽  
Preliminary Test ◽  
Elastic Stability ◽  
Thermally Induced ◽  
Package Design ◽  
Silicone Gels ◽  
Low Modulus ◽  
Supporting Frame

In order to combine the merits of epoxies, which provide good environmental and mechanical protection, and the merits of silicone gels, resulting in low stresses, one can use an encapsulation version, where a low modulus gel is utilized as a major encapsulant, while epoxy is applied as a protecting cap. Such an encapsulation version is currently under consideration, parallel with a metal cap version, for the Advanced VLSI package design which is being developed at AT&T Bell Laboratories. We recommend that the coefficient of thermal expansion for the epoxy be somewhat smaller than the coefficient of thermal expansion for the supporting frame. In this case the thermally induced displacements would result in a desirable tightness in the cap/frame interface. This paper is aimed at the assessment of stresses, which could arise in the supporting frame and in the epoxy cap at low temperatures. Also, the elastic stability of the cap, subjected to compression, is evaluated. The calculations were executed for the Advanced VLSI package design and for a Solder Test Vehicle (STV), which is currently used to obtain preliminary information regarding the performance of the candidate encapsulants. It is concluded that in order to avoid buckling of the cap, the latter should not be thinner than 15 mils (0.40 mm) in the case of VLSI package design and than 17.5 mils (0.45 mm) in the case of STV. At the same time, the thickness of the cap should not be greater than necessary, both for smaller stresses in the cap and for sufficient undercap space, required for wirebond encapsulation. The obtained formulas enable one to evaluate the actual and the buckling stresses. Preliminary test data, obtained by using STV samples, confirmed the feasibility of the application of an epoxy cap in a flip-chip package design.

Package Design Optimization of the Fan-out Interposer System

2021 ◽  
Author(s):  
Sang Kyu Kim ◽  
Sangwook Park ◽  
Seung Yong Cha ◽  
Sang Nam Jung ◽  
Gyongbum Kim ◽  
...  
Keyword(s):  
Design Optimization ◽  
Package Design

A Non-Through Silicon Via 1000+ IO Package On Package Solution For Wide IO Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000094-000099 ◽  
Author(s):  
Laura Mirkarimi ◽  
Rajesh Katkar ◽  
Ron Zhang ◽  
Rey Co ◽  
Zhijun Zhao
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
Design Optimization ◽  
High Yield ◽  
Element Analysis ◽  
Package Design ◽  
Simulation Methodology ◽  
Structural Modifications ◽  
Simulation Tools ◽  
Large Bandwidth

We are developing a new solution for wide I/O package on package applications, which is Bond Via Array (BVA) technology. The prototype vehicle built in this study has 1020 I/O's at a pitch of 0.24 mm with a high aspect ratio of approximately 10:1 and is ≤1.4 mm tall. PoP applications require large bandwidth and thinner packages challenging package developers to address warpage control for high yield processes. The design optimization of this package was established through rigorous finite element analysis of materials selection and structural modifications. The simulation methodology was validated by measuring the warpage as a function of temperature for the experimental prototypes. The details for the simulation and verification processes for the wide I/O process will be discussed. The variation between finite element analysis predictions and the experimental builds was ~10%, which allowed us to complete package design optimization with our simulation tools. The prototype build includes a standard and a low CTE substrate.

Procedure for design optimization of a T-cap flip chip package

2002 ◽  
Vol 42 (12) ◽  
pp. 1903-1911 ◽  
Author(s):  
Chin-Yu Ni ◽  
De-Shin Liu ◽  
Ching-Yang Chen
Keyword(s):  
Design Optimization ◽  
Flip Chip

Regional Segregation With Spatial Considerations-Based Analytical Filling Time Model for Non-Newtonian Power-Law Underfill Fluid in Flip-Chip Encapsulation

2019 ◽  
Vol 141 (4) ◽  
Author(s):  
Fei Chong Ng ◽  
Aizat Abas ◽  
M. Z. Abdullah
Keyword(s):  
Power Law ◽  
Flip Chip ◽  
Current Model ◽  
Process Time ◽  
Time Model ◽  
Package Design ◽  
Absolute Value ◽  
Filling Time ◽  
Underfill Flow ◽  
Encapsulation Process

Abstract This paper presents a new analytical filling time model to predict the flow of non-Newtonian underfill fluid during flip-chip encapsulation process. The current model is formulated based on the regional segregation approach, instead of the conventional porous media approximation. In this approach, the filling times were computed separately at different filling stages, before being summed up till the required filling distance. The non-Newtonian property of underfill fluid is modeled using the conventional power-law constitutive equation. Additionally, the spatial aspects of the underfill flow were incorporated into the present analysis. For instance, the evolution of underfill menisci from convex to concave was analytically developed and the contact line jump (CLJ) criterion was improved using minimal flow assumption. Upon validated with three distinct past underfill experiments, the current analytical model is found to have the best performance as it predicted the filling times with the least discrepancy among other existing filling time models. Quantitatively, the discrepancies were averagely reduced by an absolute value of at least 8.68% and 4.90%, respectively, for the first two set of validation studies. Generally, this model is particularly useful in manufacturing lines to estimate the process time of flip-chip underfill, as well as for the optimizations of process and package design.

A Theoretical Analysis of the Concept of Critical Clearance Toward a Design Methodology for the Flip-Chip Package

2007 ◽  
Vol 129 (4) ◽  
pp. 473-478 ◽  
Author(s):  
J. W. Wan ◽  
W. J. Zhang ◽  
D. J. Bergstrom
Keyword(s):  
Flip Chip ◽  
Solder Bump ◽  
Flow Characteristics ◽  
Quantitative Relation ◽  
Package Design ◽  
Solder Bumps ◽  
Filling Time ◽  
Encapsulation Process ◽  
Advanced Packaging ◽  
Gap Height

In this article, we present a theoretical study on the concept known as critical clearance for flip-chip packages. The critical clearance phenomenon was first observed in an experiment reported by Gordon et al. (1999, “A Capillary-Driven Underfill Encapsulation Process,” Advanced Packaging, 8(4), pp. 34–37). When the clearance is below a critical value, filling time begins to increase dramatically, and when the clearance is above this value, the influence of clearance on filling time is insignificant. Therefore, the optimal solder bump density in a flip-chip package should be one with a clearance larger than the critical clearance. The contribution of our study is the development of a quantitative relation among package design features, flow characteristics, and critical clearance based on an analytical model we developed and reported elsewhere. This relation is further used to determine critical clearance given a type of underfill material (specifically the index n of the power-law constitutive equation), the solder bump pitch, and the gap height; further the flip-chip package design can be optimized to make the actual clearance between solder bumps greater than its corresponding critical clearance.

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