Reliability and process characterization of electroless Nickel-Gold/Solder flip chip interconnect technology

Author(s):  
S. Wiegele ◽  
P. Thompson ◽  
P. Lee ◽  
E. Ramsland
Author(s):  
Gwee Hoon Yen ◽  
Ng Kiong Kay

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.


Fuel ◽  
2021 ◽  
pp. 122670
Author(s):  
Yuebing Zhang ◽  
Quangui Li ◽  
Qianting Hu ◽  
Cheng Zhai ◽  
Mingyang Song ◽  
...  

2015 ◽  
Author(s):  
Aneliya KARADZHINOVA ◽  
Anton Nolvi ◽  
Jaakko Härkönen ◽  
Panja Luukka ◽  
Teppo Mäenpää ◽  
...  

2014 ◽  
Vol 20 (4-5) ◽  
pp. 861-867 ◽  
Author(s):  
T. Waber ◽  
W. Pahl ◽  
M. Schmidt ◽  
G. Feiertag ◽  
S. Stufler ◽  
...  

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