[1992] Proceedings International Conference on Wafer Scale Integration
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Published By IEEE Comput. Soc. Press

0818624825

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Implementation of a defect-tolerant large area monolithic multiprocessor system

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171793 ◽

2003 ◽

Cited By ~ 7

Author(s):

M. Kuboschek ◽

H.-J. Iden ◽

U. Jagau ◽

J. Otterstedt

Keyword(s):

Multiprocessor System ◽

Large Area

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Bit serial fault tolerant architectures for convolution and polynomial evaluation

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171823 ◽

2003 ◽

Author(s):

L. Breveglieri ◽

L. Dadda ◽

D. Sciuto

Keyword(s):

Fault Tolerant ◽

Polynomial Evaluation ◽

Bit Serial

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Keynote address: critical issues in wafer scale design

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171788 ◽

2003 ◽

Author(s):

J.I. Raffel

Keyword(s):

Keynote Address ◽

Wafer Scale ◽

Critical Issues ◽

Scale Design

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Process characterization and yield assessment in hybrid wafer scale integration

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171806 ◽

2003 ◽

Cited By ~ 6

Author(s):

R. Turner ◽

M. Robinson ◽

H. Dearman ◽

D.J. Pedder ◽

A.G. Munns ◽

...

Keyword(s):

Wafer Scale ◽

Process Characterization ◽

Wafer Scale Integration ◽

Scale Integration

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The impact of the declining cost per MIPS

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171789 ◽

2003 ◽

Author(s):

D.L. Peltzer

Keyword(s):

The Impact

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Design and evaluation of wafer scale clock distribution

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171808 ◽

2003 ◽

Cited By ~ 12

Author(s):

D.C. Keezer ◽

V.K. Jain

Keyword(s):

Clock Distribution ◽

Wafer Scale

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HASP-1002: a hybrid wafer scale associative string processor

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171803 ◽

2003 ◽

Cited By ~ 7

Author(s):

I.P. Jalowiecki ◽

J.J. Reche ◽

C. Habiger ◽

R.M. Lea

Keyword(s):

Wafer Scale

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Design and analysis of defect tolerant hierarchical sorting networks

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171816 ◽

2003 ◽

Author(s):

Sy-Yen Kuo ◽

Sheng-Chiech Liang

Keyword(s):

Sorting Networks

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Processor array self-reconfiguration by neural networks

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171796 ◽

2003 ◽

Cited By ~ 2

Author(s):

J.S. Yih ◽

P. Mazumder

Keyword(s):

Neural Networks ◽

Processor Array

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DFGs for synthesis of alternative architectures: Node activation synthesis

[1992] Proceedings International Conference on Wafer Scale Integration ◽

10.1109/icwsi.1992.171818 ◽

2003 ◽

Cited By ~ 1

Author(s):

A. Antola ◽

F. Distante

Keyword(s):

Node Activation

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[1992] Proceedings International Conference on Wafer Scale IntegrationLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE Comput. Soc. Press

Implementation of a defect-tolerant large area monolithic multiprocessor system

Bit serial fault tolerant architectures for convolution and polynomial evaluation

Keynote address: critical issues in wafer scale design

Process characterization and yield assessment in hybrid wafer scale integration

The impact of the declining cost per MIPS

Design and evaluation of wafer scale clock distribution

HASP-1002: a hybrid wafer scale associative string processor

Design and analysis of defect tolerant hierarchical sorting networks

Processor array self-reconfiguration by neural networks

DFGs for synthesis of alternative architectures: Node activation synthesis

[1992] Proceedings International Conference on Wafer Scale Integration
Latest Publications