1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon
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Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552428 ◽

2002 ◽

Cited By ~ 4

Author(s):

C.A. Maier ◽

H. Greub ◽

B. Philhower ◽

S. Steidl ◽

A. Garg ◽

...

Keyword(s):

High Speed ◽

Digital Circuits

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Fault-tolerant cube-connected cycles capable of quick broadcasting

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552443 ◽

2002 ◽

Cited By ~ 3

Author(s):

N. Tsuda

Keyword(s):

Fault Tolerant ◽

Cube Connected Cycles

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Tradeoffs in chip and substrate complexity and cost for field programmable multichip modules

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552429 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Darnauer ◽

Wayne Wei-Ming Dai

Keyword(s):

Multichip Modules ◽

Field Programmable

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A wafer-scale MEMS and analog VLSI system for active drag reduction

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552410 ◽

2002 ◽

Author(s):

B. Gupta ◽

R. Goodman ◽

Fukang Jiang ◽

T. Tsao ◽

Yu-Chong Tai ◽

...

Keyword(s):

Drag Reduction ◽

Analog Vlsi ◽

Wafer Scale ◽

Vlsi System ◽

Active Drag

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Testability analysis of pipelined data paths

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552433 ◽

2002 ◽

Author(s):

G. Buonanno ◽

F. Ferrandi ◽

D. Sciuto

Keyword(s):

Testability Analysis

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A VLSI architecture for an 80 Gb/s ATM switch core

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552406 ◽

2002 ◽

Cited By ~ 8

Author(s):

P. Andersson ◽

C. Svensson

Keyword(s):

Vlsi Architecture ◽

Atm Switch

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Reduced complexity SIMD-class architectures

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552442 ◽

2002 ◽

Author(s):

M.A. Glover ◽

A. Rucinski ◽

W.T. Miller

Keyword(s):

Reduced Complexity

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Yield analysis of a novel scheme for defect-tolerant memories

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552434 ◽

2002 ◽

Cited By ~ 3

Author(s):

I. Koren ◽

Z. Koren

Keyword(s):

Yield Analysis

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Fast yield prediction for accurate costing of ICs

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552435 ◽

2002 ◽

Cited By ~ 1

Author(s):

G.A. Allan ◽

A.J. Walton

Keyword(s):

Yield Prediction

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Performance analysis of a 10-Gbit/s digital switch on MCM

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon ◽

10.1109/iciss.1996.552431 ◽

2002 ◽

Cited By ~ 3

Author(s):

C. Truzzi ◽

E. Beyne ◽

E. Ringoot

Keyword(s):

Performance Analysis

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1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in SiliconLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

Embedded at-speed testing schemes with low overhead for high speed digital circuits on multi-chip modules

Fault-tolerant cube-connected cycles capable of quick broadcasting

Tradeoffs in chip and substrate complexity and cost for field programmable multichip modules

A wafer-scale MEMS and analog VLSI system for active drag reduction

Testability analysis of pipelined data paths

A VLSI architecture for an 80 Gb/s ATM switch core

Reduced complexity SIMD-class architectures

Yield analysis of a novel scheme for defect-tolerant memories

Fast yield prediction for accurate costing of ICs

Performance analysis of a 10-Gbit/s digital switch on MCM

1996 Proceedings. Eighth Annual IEEE International Conference on Innovative Systems in Silicon
Latest Publications