On the development of Software-Based Self-Test methods for VLIW processors

2012 ◽  
Author(s):  
D. Sabena ◽  
M. Sonza Reorda ◽  
L. Sterpone
Keyword(s):  
Test Methods ◽  
Vliw Processors ◽  
Self Test

scholarly journals Research trends and challenges on DAC testing

ACTA IMEKO ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 46
Author(s):  
Eulalia Balestrieri ◽  
Pasquale Daponte ◽  
Luca De Vito ◽  
Francesco Picariello ◽  
Sergio Rapuano ◽  
...  
Keyword(s):  
Measurement Uncertainty ◽  
Research Work ◽  
Test Methods ◽  
Research Trends ◽  
Test Time ◽  
Essential Information ◽  
Digital To Analog Converters ◽  
Wide Range ◽  
Effective Performance ◽  
Self Test

<p class="Abstract"><span lang="EN-US">Today a very wide range of different applications relies on the Digital to Analog Converters (DACs). Different DAC architectures have been developed in the years and several different specifications exist to quantify their effective performance, essential information to verify the requirement fulfilling and the DAC suitability for the specific application.  As a result, DAC testing has assumed and continues to assume increasing importance. Main testing challenges include the reduction of the test time and cost, the measurement uncertainty computation and facing with the emerging Built-In Self-Test (BIST) solutions. To unambiguously clarify DAC terms, definitions and test methods the IEEE Std. 1658 has been developed and is currently under revision. To highlight the trends and issues also providing useful information for the revision of the standard, the paper presents an overview of the recent research work dealing with the DAC testing.</span></p><p class="Abstract"><span lang="EN-US"> </span></p>

scholarly journals BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

2018 ◽  
Vol 1 (4) ◽  
Author(s):  
Hadi Jahanirad ◽  
Hanieh Karam
Keyword(s):  
Cmos Technology ◽  
Test Methods ◽  
Leakage Power ◽  
Digital Systems ◽  
Area Overhead ◽  
Logic Block ◽  
Fpga Chip ◽  
Simulation Results ◽  
Self Test ◽  
Built In Self Test

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

Two self-test methods applied to an inertial system problem

1975 ◽  
Vol 12 (7) ◽  
pp. 434-437 ◽  
Author(s):  
Alan S. Willsky ◽  
John J. Deyst ◽  
Bard S. Crawford
Keyword(s):  
Test Methods ◽  
Inertial System ◽  
Self Test

Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods

2011 ◽  
Vol 28 (1) ◽  
pp. 27-38 ◽  
Author(s):  
Yi Lou ◽  
Zhuo Yan ◽  
Fan Zhang ◽  
Paul D. Franzon
Keyword(s):  
Test Methods ◽  
Through Silicon Via ◽  
Self Test

Intelligent Monitoring Design and Research of Modern Instrumentation Failure Alarm

2012 ◽  
Vol 214 ◽  
pp. 534-537
Author(s):  
Shu Fang Yu ◽  
Xiao Ping Shi ◽  
Xiu Liang Huang
Keyword(s):  
Intelligent Design ◽  
Test Methods ◽  
Normal Operation ◽  
Intelligent Monitoring ◽  
Monitoring Design ◽  
Test Circuit ◽  
State Test ◽  
Self Test ◽  
Instrumentation Failure ◽  
Modern Instrumentation

The instrumentation is a complexity of the whole system composed by many circuit modules. In order to achieve the detection to the entire system, when the overall system design, the designer must design circuits with judge and test methods suitable for a variety of levels in the case of considering to enables various modules carry on the wrong judgment and state test. This will provide the capabilities of intelligent monitoring and detection for the normal operation of the whole system. This paper has briefly introduced the development trends of modern instrumentation, analyzed the classification level of the failure alarm, given the general intelligent failure alarm circuit and self-test circuit, and provided a theoretical basis and practical reference for the studying of intelligent design of the failure alarm in a variety of instrumentation.

Sign in / Sign up

Export Citation Format

Share Document