scholarly journals A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Xiaohui Fan ◽  
Yangbo Wu ◽  
Hengfeng Dong ◽  
Jianping Hu
Keyword(s):  
Vlsi Design ◽  
Leakage Power ◽  
Total Power ◽  
Sleep Mode ◽  
Power Gating ◽  
Data Retention ◽  
Flip Flop ◽  
Low Leakage ◽  
Area Overhead ◽  
Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

scholarly journals Leakage Power Minimization Using Gating Technique In FPGA Controlled Device

2013 ◽  
Vol 2 (04) ◽  
pp. 07-12
Author(s):  
Mr. Sagar Kothawade
Keyword(s):  
Power Consumption ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Power Gating ◽  
Low Leakage ◽  
Look Up Table ◽  
Area Overhead ◽  
Total Power Consumption

FPGA based controlled devices are widely used in integrated chip sector provided the power consumed by such devices should be low. Leakage power takes vital part in contributing towards the total power consumption. This research work concentrates in proposing a power gating technique based on look up table approach. The novelty of this approach is that common look up tables are employed for asynchronous architectures for each leaf node. Due to this the leakage power and the total area overhead can be minimized. The proposed architecture is simulated through M-Power analysis and simulator tool for leaf nodes and efficiently utilizes H-tree methodology to minimize area. The reduction in number of look up tables leads to 45% to 50% reduction in leakage power of FPGA device.

LOW-LEAKAGE FLIP-FLOPS BASED ON DUAL-THRESHOLD AND MULTIPLE LEAKAGE REDUCTION TECHNIQUES

2011 ◽  
Vol 20 (01) ◽  
pp. 147-162 ◽  
Author(s):  
WEIQIANG ZHANG ◽  
LI SU ◽  
YU ZHANG ◽  
LINFENG LI ◽  
JIANPING HU
Keyword(s):  
Total Power ◽  
High Threshold ◽  
Leakage Currents ◽  
Flip Flop ◽  
Leakage Reduction ◽  
Low Leakage ◽  
Reduction Techniques ◽  
Low Threshold ◽  
Critical Paths ◽  
P Type

The scaling of transistor sizes has resulted in dramatic increase of leakage currents. The sub-threshold and gate leakages have now become a major contributor to total power dissipations. This paper presents two flip-flops based on dual-threshold CMOS and multiple leakage reduction techniques to reduce their leakage dissipations. In the DT-TG FF (Dual-Threshold Transmission Gate Flip-Flop), some transistors on non-critical paths use high-threshold devices to reduce their leakage currents, while the other transistors on critical paths use low-threshold devices to maintain performance. The MLRT FF (Multiple Leakage Reduction Technique Flip-Flop) uses P-type CMOS techniques, MTCMOS (Multi-Threshold CMOS) power-gating and dual-threshold technique to reduce both sub-threshold and gate leakage dissipations. Taken as an example, a practical sequential system realized with the two low-leakage flip-flops is demonstrated using a mode-5 × 5 × 5 counter. The simulation results show that the two flip-flops achieve considerable leakage reductions.

Various Logically Optimized D Flip Flop Circuits-A Comparative Study in Submicron Technology

2015 ◽  
Vol 4 (2) ◽  
Author(s):  
Abhijit Asthana ◽  
Shyam Akashe
Keyword(s):  
Comparative Study ◽  
Power Dissipation ◽  
Leakage Power ◽  
Simulation Test ◽  
Flip Flop ◽  
Chip Area ◽  
Low Leakage ◽  
Signal Systems ◽  
To Come ◽  
Power Delay Product

D-Flip Flop (D_FF) is a very important component of various digital, analog and mixed signal systems and designs. It is obvious to come up with optimized D_FF, that cater the needs of low leakage power, less power dissipation, less chip area on the chip and low delays. This paper presents a comparative study of various logically optimized circuits of D_FF using 8T, 11T, 12T and conventional 18T D_FF. The simulation, test circuits, schematics & layouts etc are done on Cadence Virtuoso tool in 180 nm technology. Designs are compared on grounds of power dissipation, leakage power, delays and power delay product.

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power

2016 ◽  
Vol 25 (05) ◽  
pp. 1650044 ◽  
Author(s):  
Debanjali Nath ◽  
Priyanka Choudhury ◽  
Sambhu Nath Pradhan
Keyword(s):  
Power Supply ◽  
Critical Path ◽  
Hybrid Approach ◽  
Leakage Power ◽  
Total Power ◽  
Power Gating ◽  
Path Delay ◽  
Clock Period ◽  
Finite State ◽  
A New Technique

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.

scholarly journals DESIGN &ANALYSIS OF DUAL STACK METHOD FOR FUTURE TECHNOLOGIES

2015 ◽  
pp. 245-250
Author(s):  
P. RAVALI TEJA ◽  
D. AJAY KUMAR
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Vlsi Design ◽  
Design Analysis ◽  
Leakage Power ◽  
Power Gating ◽  
Comparison Results ◽  
Different Types ◽  
Low Power Vlsi Design ◽  
Future Technologies

As low power circuits are most popular now a days as the scaling increase the leakage power in the circuit also increases rapidly so for removing these kind of leakages and to provide a better power efficiency we are using many types of power gating techniques. In this paper we are going to analyse the different types of flip-flops using different types of power gated circuits using low power VLSI design techniques and we are going to display the comparison results between different nanometer technologies. The NMOS1mulations were done using Microwind Layout Editor & DSCH software and the results were given below.

scholarly journals DESIGN OF A NEW DOUBLE PULSE LATCH FLIP FLOP

2013 ◽  
pp. 149-152
Author(s):  
Nishant Tripathi ◽  
Amit Kumar ◽  
Sanjay Singh ◽  
Dhramjeet Yadav
Keyword(s):  
Pulse Generator ◽  
Cmos Technology ◽  
Leakage Power ◽  
Double Pulse ◽  
Total Power ◽  
Feature Size ◽  
Flip Flop ◽  
Timing Property ◽  
Total Power Consumption ◽  
Scale Down

This paper presents a new double pulse flip flop, which is composed of a pulse generator and latch part. DPLFF consumes less power and few transistor compare to other flip-flop. As feature size of the CMOS technology continues to scale down, leakage power has become an ever-increasing important part of the total power consumption of a chip. Double pulsed latch flip flop faster than other flip flop. This design features consumes less power. In this flip flop we modified the pulse generator to suit the circuit. The double pulse latch flip-flop has symmetric timing property. TSPICE simulation result at a frequency of 400MHz shows that proposed DPLFF consume less power compare to DPSCRFF.

scholarly journals DESIGN APPROACHES FOR LOW POWER- LOW AREA D FLIP FLOP S IN NANO TECHNOLOGY

2013 ◽  
pp. 231-236
Author(s):  
FAYAZ KHAN ◽  
SIREESH BABU
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Vital Role ◽  
Leakage Power ◽  
Total Power ◽  
Short Channel ◽  
Qualitative Comparison ◽  
Flip Flop ◽  
Low Area ◽  
Total Power Consumption

This paper enumerates design of D flip flop with low power and low area for low power applications, for that analysis of various D-flip flops for low power dissipation ,area and delays is carried out at 0.12um to achieve low power, low-area the technology is scaled down to nanometer ranges, due to shrinking process, the leakage power tends to play a vital role in total power consumption at nano meter technology. In this paper, different D flip flop circuits are designed using Berkeley Short Channel Insulated Gate MOSFET (BSIM4) model equations., in this paper to reduce leakage power at 90nm 70nm and 50nm we implement leakage power reduction techniques six techniques are considered they are namely Sleep transistor, sleepy stack, Dual sleep ,Dual stack Forced Transistor sleep (FTS) and Sleepy keeper From the results, it is observed that SLEEP TRANSISTOR, and SLEEPY KEEPER.FORCED TRANSISTOR SLEEP techniques produces lower power dissipation than the other techniques , in this paper a qualitative comparison is done with the help of Dsch,, Micro wind Simulation tools, this paper concludes that a leakage reduction technique produce different power optimization levels for different architectures and employing a suitable technique for a particular architecture will be an effective way of reducing the leakage current and thereby static power.

Low Leakage Optimization Techniques for Multi-threshold CMOS Circuits

2020 ◽  
Vol 10 (5) ◽  
pp. 696-708
Author(s):  
Rumi Rastogi ◽  
Sujata Pandey ◽  
Mridula Gupta
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
High Speed ◽  
Room Temperature ◽  
Leakage Power ◽  
Optimization Techniques ◽  
Power Gating ◽  
Low Leakage ◽  
Charge Recycling ◽  
A New Technique

Background: With the reducing size of the devices, the leakage power has also increased exponentially in the nano-scale CMOS devices. Several techniques have been devised so far to minimize the leakage power, among which, MTCMOS (power-gating) is the preferred one as it effectively minimizes the leakage power without any complexity in the circuit. However, the power-gating technique suffers from problems like transition noise and delay. In this paper, we proposed a new simple yet effective technique to minimize leakage power in MTCMOS circuits. Objective: The objective of the paper was to propose a new technique which effectively minimizes leakage power in nanoscale power-gated circuits with minimal delay, noise and area requirement so that it can well be implemented in high-speed low-power digital integrated circuits. Methods: A new power-gating structure has been proposed in this paper. The new proposed technique includes three parallel NMOS transistors with variable widths which are functional during the active mode to reduce the on-time delay. A PMOS footer with gate-bias is also connected in parallel with the NMOS footer transistors. The proposed technique has been verified through simulation in 45nm MTCMOS technology to implement a 32 bit adder circuit. Results: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduced the leakage power effectively at room temperature as well as higher temperatures. The reactivation noise produced by the proposed technique minimized by 98.7%, 64.8%, 62.07% and 24.47% as compared to the parallel transistor, variable-width, charge-recycling and the modified-charge recycling techniques respectively at room temperature.The reactivation energy of the proposed technique also minimized by 77.by 77.67%, 55.8%, 45.1%, and 18.32% with respect to the parallel transistor, variable-width, CR and Modified-CR techniques, respectively. Conclusion: The proposed technique offers significant reduction in leakage power, reactivation noise and reactivation energy. The technique reduces the leakage power effectively at room temperature as well as at higher temperatures. Since the delay and area overhead of the proposed structure is minimal, hence it can be easily implemented in high-speed low-power digital circuits.

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