Hybrid delay scan: a low hardware overhead scan-based delay test technique for high fault coverage and compact test sets

Proceedings Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2004.1269074 ◽

2004 ◽

Cited By ~ 52

Author(s):

Seongmoon Wang ◽

Xiao Liu ◽

S.T. Chakradhar

Keyword(s):

Fault Coverage ◽

Delay Test ◽

Test Technique ◽

Hardware Overhead ◽

Test Sets ◽

Compact Test

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Test point insertion for compact test sets

Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159) ◽

10.1109/test.2000.894217 ◽

2002 ◽

Cited By ~ 28

Author(s):

M.J. Geuzebroek ◽

J.T. van der Linden ◽

A.J. van de Goor

Keyword(s):

Test Point ◽

Test Point Insertion ◽

Test Sets ◽

Compact Test

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A method to derive compact test sets for path delay faults in combinational circuits

Proceedings of IEEE International Test Conference - (ITC) ◽

10.1109/test.1993.470630 ◽

2002 ◽

Cited By ~ 27

Author(s):

J. Saxena ◽

D.K. Pradhan

Keyword(s):

Delay Faults ◽

Path Delay ◽

Combinational Circuits ◽

Path Delay Faults ◽

Test Sets ◽

Compact Test

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Compact test sets for industrial circuits

Proceedings 13th IEEE VLSI Test Symposium ◽

10.1109/vtest.1995.512661 ◽

2002 ◽

Cited By ~ 10

Author(s):

M.H. Konijnenburg ◽

J.T. van der Linden ◽

A.J. van de Goor

Keyword(s):

Test Sets ◽

Industrial Circuits ◽

Compact Test

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Generation of compact test sets with high defect coverage

2009 Design, Automation & Test in Europe Conference & Exhibition ◽

10.1109/date.2009.5090833 ◽

2009 ◽

Cited By ~ 10

Author(s):

X. Kavousianos ◽

K. Chakrabarty

Keyword(s):

Defect Coverage ◽

Test Sets ◽

Compact Test

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Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with compact test sets

Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144) ◽

10.1109/mwscas.2000.951619 ◽

2002 ◽

Author(s):

S.R. Das ◽

M. Sudarma ◽

Jingyi Liang ◽

E.M. Petriu ◽

M.H. Assaf ◽

...

Keyword(s):

Vlsi Circuits ◽

Response Data ◽

Self Testing ◽

Data Compaction ◽

Test Sets ◽

Compact Test

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Dynamic X-filling for Peak Capture Power Reduction for Compact Test Sets

Journal of Electronic Testing ◽

10.1007/s10836-014-5472-6 ◽

2014 ◽

Vol 30 (5) ◽

pp. 557-567 ◽

Cited By ~ 3

Author(s):

Stephan Eggersglüß

Keyword(s):

Power Reduction ◽

Test Sets ◽

Compact Test

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Generation of compact test sets and a design for the generation of tests with low switching activity

10.17077/etd.93exb2ob ◽

2014 ◽

Author(s):

Amit Kumar

Keyword(s):

Switching Activity ◽

Test Sets ◽

Compact Test

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Peak Capture Power Reduction for Compact Test Sets Using Opt-Justification-Fill

2013 22nd Asian Test Symposium ◽

10.1109/ats.2013.16 ◽

2013 ◽

Cited By ~ 3

Author(s):

Stephan Eggersgluss

Keyword(s):

Power Reduction ◽

Test Sets ◽

Compact Test

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High fault coverage of in-circuit IC pin faults with a vectorless test technique using parasitic transistors

Proceedings International Test Conference 1996. Test and Design Validity ◽

10.1109/test.1996.557156 ◽

2002 ◽

Cited By ~ 2

Author(s):

J. Ferguson

Keyword(s):

Fault Coverage ◽

Test Technique

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On the generation of compact test sets

2013 IEEE International Test Conference (ITC) ◽

10.1109/test.2013.6651914 ◽

2013 ◽

Cited By ~ 3

Author(s):

Amit Kumar ◽

Janusz Rajski ◽

Sudhakar M. Reddy ◽

Chen Wang

Keyword(s):

Test Sets ◽

Compact Test

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