Effective software self-test methodology for processor cores

Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2002.998361 ◽

2003 ◽

Cited By ~ 32

Author(s):

N. Kranitis ◽

A. Paschalis ◽

D. Gizopoulos ◽

Y. Zorian

Keyword(s):

Test Methodology ◽

Self Test ◽

Processor Cores

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DEFUSE: a deterministic functional self-test methodology for processors

Proceedings 18th IEEE VLSI Test Symposium ◽

10.1109/vtest.2000.843853 ◽

2002 ◽

Cited By ~ 43

Author(s):

L. Chen ◽

S. Dey

Keyword(s):

Test Methodology ◽

Self Test

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HIST: A hierarchical self test methodology for chips, boards, and systems

Journal of Electronic Testing ◽

10.1007/bf00993132 ◽

1995 ◽

Vol 6 (1) ◽

pp. 85-106 ◽

Cited By ~ 2

Author(s):

Oliver F. Haberl ◽

Thomas Kropf

Keyword(s):

Test Methodology ◽

Self Test

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A scalable software-based self-test methodology for programmable processors

10.1109/dac.2003.1219068 ◽

2004 ◽

Cited By ~ 80

Author(s):

Li Chen ◽

S. Ravi ◽

A. Raghunathan ◽

S. Dey

Keyword(s):

Test Methodology ◽

Self Test ◽

Programmable Processors ◽

Scalable Software

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Software-Based Self Test Methodology for On-Line Testing of L1 Caches in Multithreaded Multicore Architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems ◽

10.1109/tvlsi.2012.2191000 ◽

2013 ◽

Vol 21 (4) ◽

pp. 786-790 ◽

Cited By ~ 15

Author(s):

Giorgos Theodorou ◽

Nektarios Kranitis ◽

Antonis Paschalis ◽

Dimitris Gizopoulos

Keyword(s):

Multicore Architectures ◽

Test Methodology ◽

On Line ◽

Self Test

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A Software-Based Self-Test methodology for on-line testing of processor caches

2011 IEEE International Test Conference ◽

10.1109/test.2011.6139154 ◽

2011 ◽

Cited By ~ 7

Author(s):

G. Theodorou ◽

N. Kranitis ◽

A. Paschalis ◽

D. Gizopoulos

Keyword(s):

Test Methodology ◽

On Line ◽

Self Test ◽

Processor Caches

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A self-testable SiGe LNA and Built-in-Self-Test methodology for multiple performance specifications of RF amplifiers

Thirteenth International Symposium on Quality Electronic Design (ISQED) ◽

10.1109/isqed.2012.6187467 ◽

2012 ◽

Cited By ~ 1

Author(s):

Abhilash Goyal ◽

Madhavan Swaminathan ◽

Abhijit Chatterjee ◽

Duane Howard ◽

John D. Cressler

Keyword(s):

Rf Amplifiers ◽

Test Methodology ◽

Performance Specifications ◽

Self Test ◽

Built In Self Test

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Serial interface logic built in self test methodology

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT) ◽

10.1109/iemt.2008.5507795 ◽

2008 ◽

Author(s):

Kean Hong Boey ◽

Kok Sing Yap ◽

Wai Mun Ng

Keyword(s):

Serial Interface ◽

Test Methodology ◽

Self Test ◽

Built In Self Test

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Efficient Template Generation for Instruction-Based Self-Test of Processor Cores

13th Asian Test Symposium ◽

10.1109/ats.2004.39 ◽

2005 ◽

Cited By ~ 8

Author(s):

K. Kambe ◽

M. Inoue ◽

H. Fujiwara

Keyword(s):

Self Test ◽

Processor Cores

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Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology

IEEE International Conference on Test, 2005. ◽

10.1109/test.2005.1584059 ◽

2006 ◽

Author(s):

Charles H.-P. Wen ◽

L.-C. Wang ◽

Kwang-Ting Cheng ◽

Wei-Ting Liu ◽

Ji-Jan Chen

Keyword(s):

Test Generation ◽

Test Methodology ◽

Simulation Based ◽

Self Test

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A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters

13th Asian Test Symposium ◽

10.1109/ats.2004.18 ◽

2005 ◽

Cited By ~ 3

Author(s):

Hsin-Wen Ting ◽

Bin-Da Liu ◽

Soon-Jyh Chang

Keyword(s):

Time Domain ◽

Analog To Digital Converters ◽

Analog To Digital ◽

Test Methodology ◽

Self Test ◽

Built In Self Test

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