scholarly journals Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

2006 ◽  
Vol 25 (6) ◽  
pp. 1146-1154 ◽  
Author(s):  
M. Badaroglu ◽  
K. Tiri ◽  
G. Van der Plas ◽  
P. Wambacq ◽  
I. Verbauwhede ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Substrate Noise ◽  
Clock Skew ◽  
Supply Current ◽  
Optimization Methodology

Emulation of High Frequency Substrate Noise in CMOS Digital Circuits with Effects of Adjusting Clock Skew

2013 ◽  
Author(s):  
S. Shimazaki ◽  
S. Taga ◽  
T. Makita ◽  
N. Azuma ◽  
N. Miura ◽  
...  
Keyword(s):  
High Frequency ◽  
Digital Circuits ◽  
Substrate Noise ◽  
Clock Skew

Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes

2009 ◽  
Author(s):  
Wai Leng Cheong ◽  
Brian Owens ◽  
Hui En Pham ◽  
Christopher Hanken ◽  
Jim Le ◽  
...  
Keyword(s):  
Noise Reduction ◽  
Substrate Noise ◽  
Supply Noise ◽  
Sige Bicmos
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