A Joint Diagnostic Test Generation Procedure with Dynamic Test Compaction

2016 IEEE 25th Asian Test Symposium (ATS) ◽

10.1109/ats.2016.15 ◽

2016 ◽

Cited By ~ 3

Author(s):

M. Enamul Amyeen ◽

Irith Pomeranz ◽

Srikanth Venkataraman

Keyword(s):

Diagnostic Test ◽

Test Generation ◽

Dynamic Test ◽

Test Compaction ◽

Generation Procedure

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Dynamic test compaction for a random test generation procedure with input cube avoidance

2009 Asia and South Pacific Design Automation Conference ◽

10.1109/aspdac.2009.4796557 ◽

2009 ◽

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Test Generation ◽

Dynamic Test ◽

Test Compaction ◽

Random Test ◽

Generation Procedure

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A diagnostic test generation procedure based on test elimination by vector omission for synchronous sequential circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ◽

10.1109/43.845083 ◽

2000 ◽

Vol 19 (5) ◽

pp. 589-600 ◽

Cited By ~ 20

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Diagnostic Test ◽

Test Generation ◽

Sequential Circuits ◽

Synchronous Sequential Circuits ◽

Generation Procedure

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A diagnostic test generation procedure for synchronous sequential circuits based on test elimination

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) ◽

10.1109/test.1998.743306 ◽

2002 ◽

Cited By ~ 31

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Diagnostic Test ◽

Test Generation ◽

Sequential Circuits ◽

Synchronous Sequential Circuits ◽

Generation Procedure

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A diagnostic test generation procedure for combinational circuits based on test elimination

Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259) ◽

10.1109/ats.1998.741661 ◽

2002 ◽

Cited By ~ 7

Author(s):

I. Pomeranz ◽

W.K. Fuchs

Keyword(s):

Diagnostic Test ◽

Test Generation ◽

Combinational Circuits ◽

Generation Procedure

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A dynamic test compaction method on low power test generation based on capture safe test vectors

2017 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) ◽

10.1109/dft.2017.8244463 ◽

2017 ◽

Author(s):

Toshinori Hosokawa ◽

Atsushi Hirai ◽

Hiroshi Yamazaki ◽

Masayuki Arai

Keyword(s):

Low Power ◽

Test Generation ◽

Dynamic Test ◽

Power Test ◽

Test Compaction ◽

Low Power Test ◽

Test Vectors ◽

Compaction Method

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Dynamic test compaction for synchronous sequential circuits using static compaction techniques

Proceedings of Annual Symposium on Fault Tolerant Computing ◽

10.1109/ftcs.1996.534594 ◽

2002 ◽

Cited By ~ 21

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Dynamic Test ◽

Sequential Circuits ◽

Test Compaction ◽

Synchronous Sequential Circuits ◽

Static Compaction

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Search State Compatibility Based Incremental Learning Framework and Output Deviation Based X-filling for Diagnostic Test Generation

Journal of Electronic Testing ◽

10.1007/s10836-010-5142-2 ◽

2010 ◽

Vol 26 (2) ◽

pp. 165-176 ◽

Cited By ~ 8

Author(s):

Maheshwar Chandrasekar ◽

Nikhil P. Rahagude ◽

Michael S. Hsiao

Keyword(s):

Diagnostic Test ◽

Test Generation ◽

Incremental Learning ◽

Learning Framework

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Diagnostic Test Generation for Arbitrary Faults

2006 IEEE International Test Conference ◽

10.1109/test.2006.297647 ◽

2006 ◽

Cited By ~ 14

Author(s):

Naresh Bhatti ◽

R.D. Blanton

Keyword(s):

Diagnostic Test ◽

Test Generation

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A new approach to test generation and test compaction for scan circuits

2003 Design, Automation and Test in Europe Conference and Exhibition ◽

10.1109/date.2003.1253735 ◽

2003 ◽

Cited By ~ 12

Author(s):

I. Pomeranz ◽

S.M. Reddy

Keyword(s):

Test Generation ◽

New Approach ◽

Test Compaction ◽

Scan Circuits

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Output-Dependent Diagnostic Test Generation

2010 23rd International Conference on VLSI Design ◽

10.1109/vlsi.design.2010.13 ◽

2010 ◽

Cited By ~ 11

Author(s):

Irith Pomeranz ◽

Sudhakar M. Reddy

Keyword(s):

Diagnostic Test ◽

Test Generation

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