A diagnostic test generation procedure based on test elimination by vector omission for synchronous sequential circuits
2000 ◽
Vol 19
(5)
◽
pp. 589-600
◽
2007 ◽
Vol 174
(4)
◽
pp. 83-93
Keyword(s):
Keyword(s):
1996 ◽
Vol 15
(7)
◽
pp. 831-843
◽
Keyword(s):