Test Infrastructure Development and Test Scheduling of 3D-Stacked ICs under Resource and Power Constraints

2015 ◽  
Author(s):  
Rajit Karmakar ◽  
Aditya Agarwal ◽  
Santanu Chattopadhyay
Keyword(s):  
Test Scheduling ◽  
Infrastructure Development ◽  
Power Constraints

Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints

2004 ◽  
Vol 20 (1) ◽  
pp. 61-78 ◽  
Author(s):  
Valentin Mureşan ◽  
Xiaojun Wang ◽  
Valentina Mureşan ◽  
Mircea Vlăduţiu
Keyword(s):  
Test Scheduling ◽  
Power Constraints ◽  
Block Test

Test scheduling algorithm for core-based multi-core 3D stacked ICs under power constraints

2013 ◽  
Vol 26 (7) ◽  
pp. 591-596
Author(s):  
Wei Wang ◽  
Zhuowei Lin ◽  
Tian Chen ◽  
Jun Liu ◽  
Fang Fang ◽  
...  
Keyword(s):  
Scheduling Algorithm ◽  
Test Scheduling ◽  
Power Constraints

A SIMULATED ANNEALING ALGORITHM FOR SYSTEM-ON-CHIP TEST SCHEDULING WITH, POWER AND PRECEDENCE CONSTRAINTS

2006 ◽  
Vol 06 (04) ◽  
pp. 511-530 ◽  
Author(s):  
HAIDAR M. HARMANANI ◽  
HASSAN A. SALAMY
Keyword(s):  
Simulated Annealing ◽  
Simulated Annealing Algorithm ◽  
System On Chip ◽  
Precedence Constraints ◽  
Test Scheduling ◽  
Optimal Test ◽  
Power Constraints ◽  
Soc Test ◽  
On Chip ◽  
Minimum System

This paper presents an efficient method to determine minimum system-on-chip (SOC) test schedules with precedence and power constraints based on simulated annealing. The problem is solved using a partitioned testing scheme with run to completion that minimizes the number of idle test slots. The method can handle SOC test scheduling with and without power constraints in addition to precedence constraints that preserve desirable orderings among tests. We present experimental results for various SOC examples that demonstrate the effectiveness of the method. The method achieved optimal test schedules in all attempted cases in a short CPU time.

Sign in / Sign up

Export Citation Format

Share Document