Diagnosing Resistive Open Faults Using Small Delay Fault Simulation

2013 ◽  
Author(s):  
Koji Yamazaki ◽  
Toshiyuki Tsutsumi ◽  
Hiroshi Takahashi ◽  
Yoshinobu Higami ◽  
Hironobu Yotsuyanagi ◽  
...  
Keyword(s):  
Fault Simulation ◽  
Delay Fault ◽  
Small Delay ◽  
Open Faults

scholarly journals GPU-Accelerated Small Delay Fault Simulation

2015 ◽  
Author(s):  
Eric Schneider ◽  
Stefan Holst ◽  
Michael A. Kochte ◽  
Xiaoqing Wen ◽  
Hans-Joachim Wunderlich
Keyword(s):  
Fault Simulation ◽  
Delay Fault ◽  
Small Delay

scholarly journals Impact of Resistive Open Faults on Inverter Chain and 7t Sram

2019 ◽  
Vol 8 (3) ◽  
pp. 559-563
Keyword(s):  
Integrated Circuit ◽  
Research Work ◽  
Cell Design ◽  
Delay Fault ◽  
Dynamic Power ◽  
Sram Cell ◽  
Open Faults ◽  
The Impact ◽  
Interconnection Lines

An aggressive scaling of the technology and the increasing the number of the transistor counts are the major challenge of the design of the Integrated Circuit (IC). As well as interconnection lines and resistive opens have become a problem in modern nanometre technologies. The resistive open faults denote degradation in the connectivity within a circuit’s interconnects because of unavoidable manufacturing failures in both current and developing technologies. The resistive open fault is an imperfect circuit connection that can be modelled as a defect resistor between two circuit nodes. The Resistive open faults will not cause function fault immediately. But, it will cause the delay fault and cannot employ the design of voltage to survey. In this research, find the impact of resistive open fault in the 7- Transistor (7T) SRAM cell design and inverter chain. The proposed 7T SRAM cell design and inverter chain is implemented in 45nm technology with cadence library. The main objective of this proposed research work is to efficiently detect impact of resistive open faults and reduces delay and static and dynamic power of 7T SRAM cell design and inverter chain.

Transition delay fault simulation with parallel critical path back-tracing and 7-valued algebra

2015 ◽  
Vol 39 (8) ◽  
pp. 1130-1138
Author(s):  
Jaak Kõusaar ◽  
Raimund Ubar ◽  
Sergei Devadze ◽  
Jaan Raik
Keyword(s):  
Critical Path ◽  
Fault Simulation ◽  
Delay Fault ◽  
Transition Delay
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