scholarly journals Defect Coverage-Driven Window-Based Test Compression

2010 ◽  
Author(s):  
Xrysovalantis Kavousianos ◽  
Krishnendu Chakrabarty ◽  
Emmanouil Kalligeros ◽  
Vasileios Tenentes
Keyword(s):  
Defect Coverage ◽  
Test Compression

Addressing Defect Coverage through Generating Test Vectors for Transistor Defects

2009 ◽  
Vol E92-A (12) ◽  
pp. 3128-3135
Author(s):  
Yoshinobu HIGAMI ◽  
Kewal K. SALUJA ◽  
Hiroshi TAKAHASHI ◽  
Shin-ya KOBAYASHI ◽  
Yuzo TAKAMATSU
Keyword(s):  
Defect Coverage ◽  
Test Vectors

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

scholarly journals Machine Learning-based Defect Coverage Boosting of Analog Circuits under Measurement Variations

2020 ◽  
Vol 25 (5) ◽  
pp. 1-27
Author(s):  
Nektar Xama ◽  
Martin Andraud ◽  
Jhon Gomez ◽  
Baris Esen ◽  
Wim Dobbelaere ◽  
...  
Keyword(s):  
Machine Learning ◽  
Analog Circuits ◽  
Defect Coverage

Design of Test Compression for Multiple Scan Chains Circuits

2021 ◽  
Author(s):  
D Manasa Manikya ◽  
Marala Jagruthi ◽  
Rana Anjum ◽  
Ashok Kumar K
Keyword(s):  
Test Compression ◽  
Multiple Scan ◽  
Scan Chains
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