2009 IEEE International High Level Design Validation and Test Workshop
Latest Publications

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9781424448234

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RTL DFT techniques to enhance defect coverage for functional test sequences

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340161 ◽

2009 ◽

Cited By ~ 3

Author(s):

Hongxia Fang ◽

Krishnendu Chakrabarty ◽

Hideo Fujiwara

Keyword(s):

Functional Test ◽

Defect Coverage

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PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340174 ◽

2009 ◽

Cited By ~ 3

Author(s):

Jeff Hao ◽

Valeria Bertacco

Keyword(s):

Static Analysis ◽

Power Attacks

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Learning from constraints for formal property checking

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340176 ◽

2009 ◽

Author(s):

In-Ho Moon ◽

Kevin Harer

Keyword(s):

Formal Property ◽

Learning From Constraints ◽

Formal Property Checking

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Committees

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340186 ◽

2009 ◽

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Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340184 ◽

2009 ◽

Cited By ~ 5

Author(s):

Miroslav N. Velev ◽

Ping Gao

Keyword(s):

Decision Procedures

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An instrumented observability coverage method for system validation

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340171 ◽

2009 ◽

Cited By ~ 5

Author(s):

Peter Lisherness ◽

Kwang-Ting Cheng

Keyword(s):

System Validation

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TG-PRO: A new model for SAT-based ATPG

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340173 ◽

2009 ◽

Cited By ~ 6

Author(s):

Huan Chen ◽

Joao Marques-Silva

Keyword(s):

New Model

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Design-for-debug for post-silicon validation: Can high-level descriptions help?

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340159 ◽

2009 ◽

Cited By ~ 4

Author(s):

Nicola Nicolici ◽

Ho Fai Ko

Keyword(s):

High Level

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Experience with widening based equivalence checking in realistic multimedia systems

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340164 ◽

2009 ◽

Cited By ~ 1

Author(s):

Sven Verdoolaege ◽

Martin Palkovic ◽

Maurice Bruynooghe ◽

Gerda Janssens ◽

Francky Catthoor

Keyword(s):

Multimedia Systems ◽

Equivalence Checking

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FLARE: A design environment for FLASH-based space applications

2009 IEEE International High Level Design Validation and Test Workshop ◽

10.1109/hldvt.2009.5340180 ◽

2009 ◽

Cited By ~ 3

Author(s):

Maurizio Caramia ◽

Stefano Di Carlo ◽

Michele Fabiano ◽

Paolo Prinetto

Keyword(s):

Design Environment ◽

Space Applications

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2009 IEEE International High Level Design Validation and Test WorkshopLatest Publications

TOTAL DOCUMENTS

H-INDEX

Published By IEEE

RTL DFT techniques to enhance defect coverage for functional test sequences

PowerRanger: Assessing circuit vulnerability to power attacks using SAT-based static analysis

Learning from constraints for formal property checking

Committees

Exploiting hierarchical encodings of equality to design independent strategies in parallel SMT decision procedures for a logic of equality

An instrumented observability coverage method for system validation

TG-PRO: A new model for SAT-based ATPG

Design-for-debug for post-silicon validation: Can high-level descriptions help?

Experience with widening based equivalence checking in realistic multimedia systems

FLARE: A design environment for FLASH-based space applications

2009 IEEE International High Level Design Validation and Test Workshop
Latest Publications