Using Programmable On-Product Clock Generation (OPCG) for Delay Test

2007 ◽  
Author(s):  
Brion Keller ◽  
Anis Uzzaman ◽  
Bibo Li ◽  
Tom Snethen
Keyword(s):  
Delay Test ◽  
Clock Generation

scholarly journals Logic Design for On-Chip Test Clock Generation - Implementation Details and Impact on Delay Test Quality

2005 ◽  
Author(s):  
M. Beck ◽  
O. Barondeau ◽  
M. Kaibel ◽  
F. Poehl ◽  
Xijiang Lin ◽  
...  
Keyword(s):  
Logic Design ◽  
Delay Test ◽  
Test Quality ◽  
Clock Generation ◽  
On Chip

Using Programmable On-Product Clock Generation (OPCG) for Delay Test

2007 ◽  
Author(s):  
Brion Keller ◽  
Anis Uzzaman ◽  
Bibo Li ◽  
Tom Snethen
Keyword(s):  
Delay Test ◽  
Clock Generation

Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test

2009 ◽  
Vol 5 (4) ◽  
pp. 520-528
Author(s):  
Anis Uzzaman ◽  
Brion Keller ◽  
Tom Snethen ◽  
Kazuhiko Iwasaki ◽  
Masayuki Arai
Keyword(s):  
Low Power ◽  
Delay Test ◽  
Clock Generation

A Study on the Usefulness of 3D T1-Weighted MR Cholangiography Through Delay Test Using GD-EOB-DTPA

2020 ◽  
Vol 30 (1) ◽  
pp. 1-9
Author(s):  
Bo-Kyung Baek ◽  
Yong-Ju Kim ◽  
Geon-Yeong Kim ◽  
Yong-Sik Bang ◽  
Hong-Uk Ku
Keyword(s):  
Delay Test ◽  
Mr Cholangiography

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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