How to Speed-Up Fault-Tolerant Clock Generation in VLSI Systems-on-Chip via Pipelining

2010 ◽  
Author(s):  
Matthias Függer ◽  
Andreas Dielacher ◽  
Ulrich Schmid
Keyword(s):  
Fault Tolerant ◽  
Clock Generation ◽  
Systems On Chip ◽  
Speed Up ◽  
On Chip

Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip

2013 ◽  
Author(s):  
Michael Dimopoulos ◽  
Yi Gang ◽  
Mounir Benabdenbi ◽  
Lorena Anghel ◽  
Nacer-Eddine Zergainoh ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Adaptive Routing ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core

scholarly journals Rigorously modeling self-stabilizing fault-tolerant circuits: An ultra-robust clocking scheme for systems-on-chip

2014 ◽  
Vol 80 (4) ◽  
pp. 860-900 ◽  
Author(s):  
Danny Dolev ◽  
Matthias Függer ◽  
Markus Posch ◽  
Ulrich Schmid ◽  
Andreas Steininger ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Systems On Chip ◽  
On Chip

scholarly journals Fault-tolerant and energy-efficient MCSoC for information processing and control

2019 ◽  
pp. 9-18
Author(s):  
Aleksandr Gruzlikov ◽  
Nikolai Kolesov ◽  
Dmitri Kostygov ◽  
Marina Tolmacheva
Keyword(s):  
Fault Tolerance ◽  
Energy Efficient ◽  
Fault Tolerant ◽  
Optimal Number ◽  
System Level ◽  
Clock Frequency ◽  
Systems On Chip ◽  
Energy Efficient Architecture ◽  
On Chip ◽  
And Control

Introduction: The majority of real complex systems are designed with respect to fault tolerance requirements. However, all theknown approaches are intended only to increase reliability. Purpose: An approach for designing fault-tolerant systems on a chip, aimednot only at increasing the reliability, but also at reducing the energy consumed by the system. Results: A two-stage approach to thedesign of fault-tolerant multicore systems-on-chip (MCSoCs) is proposed. At the first stage, an energy-efficient architecture of thedesigned system is formed. For each core used in the system, the optimal number of additional cores is determined within the frameworkof the imposed restrictions. The optimality criterion is the minimum power consumed by the system. The algorithm proposed for theformation of an energy-efficient architecture is based on the dependence of the power consumed in the system on the values of the supplyvoltage and the clock frequency. At the second stage, a procedure for diagnosing and repairing the system is developed which uses theprinciples of system-level diagnosis, involving mutual checks between the system cores. This procedure allows you to decentralize theprocess of diagnosing and restoring the system after a failure. Additionally, the article examines the organization of the communicationsubsystem based on shared memory. The study is based on a simulation conducted in order to estimate the time for making a decisionabout a failure in systems such as a lattice, torus and hypercube. Practical relevance: The proposed approach allows a system to providethe necessary values for its two most important characteristics: fault tolerance and energy efficiency. At the same time, decentralizationis ensured when making decisions about a failure and restoration. As a result, the system becomes more reliable.

scholarly journals VLSI Implementation of a Distributed Algorithm for Fault-Tolerant Clock Generation

2011 ◽  
Vol 2011 ◽  
pp. 1-23 ◽  
Author(s):  
Gottfried Fuchs ◽  
Andreas Steininger
Keyword(s):  
Fault Tolerant ◽  
Single Point ◽  
Asynchronous Design ◽  
Clock Generation ◽  
Future Technology ◽  
Novel Approach ◽  
Measurement Results ◽  
Crystal Oscillators ◽  
On Chip ◽  
Technology Nodes

We present a novel approach for the on-chip generation of a fault-tolerant clock. Our method is based on the hardware implementation of a tick synchronization algorithm from the distributed systems community. We discuss the selection of an appropriate algorithm, present the refinement steps necessary to facilitate its efficient mapping to hardware, and elaborate on the key challenges we had to overcome in our actual ASIC implementation. Our measurement results confirm that the approach is indeed capable of creating a globally synchronized clock in a distributed fashion that is tolerant to a (configurable) number of arbitrary faults. This property facilitates eliminating the clock as a single point of failure. Our solution is based on purely asynchronous design, obviating the need for crystal oscillators. It is capable of adapting to parameter variations as well as changes in temperature and power supply–properties that are considered highly desirable for future technology nodes.

Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip

2014 ◽  
Vol 38 (6) ◽  
pp. 620-635 ◽  
Author(s):  
Michael Dimopoulos ◽  
Yi Gang ◽  
Lorena Anghel ◽  
Mounir Benabdenbi ◽  
Nacer-Eddine Zergainoh ◽  
...  
Keyword(s):  
Fault Tolerant ◽  
Adaptive Routing ◽  
Link Failures ◽  
Systems On Chip ◽  
On Chip ◽  
Many Core

scholarly journals Reconciling fault-tolerant distributed computing and systems-on-chip

2011 ◽  
Vol 24 (6) ◽  
pp. 323-355 ◽  
Author(s):  
Matthias Függer ◽  
Ulrich Schmid
Keyword(s):  
Distributed Computing ◽  
Fault Tolerant ◽  
Systems On Chip ◽  
On Chip
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