Interleaving of Delay Fault Tes Data for Efficient Test Compression with Statistical Coding

2006 ◽  
Author(s):  
Kazuteru Namba ◽  
Hideo Ito
Keyword(s):  
Delay Fault ◽  
Test Compression ◽  
Efficient Test ◽  
Statistical Coding

Efficient Test Compression Configuration Selection

2021 ◽  
pp. 1-1
Author(s):  
Chong-Siao Ye ◽  
Shi-Xuan Zheng ◽  
Fong-Jyun Tsai ◽  
Chen Wang ◽  
Kuen-Jong Lee ◽  
...  
Keyword(s):  
Test Compression ◽  
Efficient Test ◽  
Configuration Selection

Power Supply Voltage Control for Eliminating Overkills and Underkills in Delay Fault Testing

2016 ◽  
Vol E99.C (10) ◽  
pp. 1219-1225
Author(s):  
Masahiro ISHIDA ◽  
Toru NAKURA ◽  
Takashi KUSAKA ◽  
Satoshi KOMATSU ◽  
Kunihiro ASADA
Keyword(s):  
Power Supply ◽  
Supply Voltage ◽  
Voltage Control ◽  
Fault Testing ◽  
Power Supply Voltage ◽  
Delay Fault ◽  
Delay Fault Testing

Enabling Electro-Optical Failure Analysis within Extreme Compression Test Architecture

2016 ◽  
Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta
Keyword(s):  
Failure Analysis ◽  
Compression Test ◽  
Test Pattern ◽  
Pattern Generation ◽  
Output Data ◽  
Test Compression ◽  
Test Loop ◽  
On Chip ◽  
Test Architecture

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

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