Efficient Constraint Extraction for Template-Based Processor Self-Test Generation

Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Journal of Electronic Testing ◽

10.1007/bf00135230 ◽

1991 ◽

Vol 2 (4) ◽

pp. 351-372 ◽

Cited By ~ 37

Author(s):

Abhijit Chatterjee ◽

Jacob A. Abraham

Keyword(s):

Test Generation ◽

Design For Testability ◽

Graph Labeling ◽

Self Test ◽

Arithmetic Units ◽

Built In Self Test

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Enhancement of Adaptive Software-Based Self Test Generation of Embedded Processors Cores

IFAC-PapersOnLine ◽

10.1016/j.ifacol.2019.12.732 ◽

2019 ◽

Vol 52 (27) ◽

pp. 56-61

Author(s):

Ján Hudec

Keyword(s):

Test Generation ◽

Embedded Processors ◽

Adaptive Software ◽

Self Test

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Automated software-based self-test generation for microprocessors

2017 MIXDES - 24th International Conference "Mixed Design of Integrated Circuits and Systems ◽

10.23919/mixdes.2017.8005252 ◽

2017 ◽

Author(s):

Artjom Jasnetski ◽

Raimund Ubar ◽

Anton Tsertov

Keyword(s):

Test Generation ◽

Self Test ◽

Automated Software

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Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology

IEEE International Conference on Test, 2005. ◽

10.1109/test.2005.1584059 ◽

2006 ◽

Author(s):

Charles H.-P. Wen ◽

L.-C. Wang ◽

Kwang-Ting Cheng ◽

Wei-Ting Liu ◽

Ji-Jan Chen

Keyword(s):

Test Generation ◽

Test Methodology ◽

Simulation Based ◽

Self Test

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An Efficient Adaptive Method of Software-Based Self Test Generation for RISC Processors

2015 4th Eastern European Regional Conference on the Engineering of Computer Based Systems ◽

10.1109/ecbs-eerc.2015.26 ◽

2015 ◽

Cited By ~ 1

Author(s):

Jan Hudec

Keyword(s):

Test Generation ◽

Adaptive Method ◽

Self Test

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Software-based self-test generation for microprocessors with high-level decision diagrams

Proceedings of the Estonian Academy of Sciences ◽

10.3176/proc.2014.1.08 ◽

2014 ◽

Vol 63 (1) ◽

pp. 48 ◽

Cited By ~ 5

Author(s):

A Jasnetski ◽

R Ubar ◽

A Tsertov ◽

M Brik

Keyword(s):

Test Generation ◽

Decision Diagrams ◽

Self Test ◽

High Level

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New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2015.56 ◽

2015 ◽

Cited By ~ 3

Author(s):

Artjom Jasnetski ◽

Jaan Raik ◽

Anton Tsertov ◽

Raimund Ubar

Keyword(s):

Test Generation ◽

Decision Diagrams ◽

Fault Models ◽

Self Test ◽

High Level

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Native mode functional test generation for processors with applications to self test and design validation

Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270) ◽

10.1109/test.1998.743296 ◽

2002 ◽

Cited By ~ 34

Author(s):

Jian Shen ◽

J.A. Abraham

Keyword(s):

Test Generation ◽

Functional Test ◽

Design Validation ◽

Self Test

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ISA Based Functional Test Generation with Application to Self-Test of RISC Processors

2006 IEEE Design and Diagnostics of Electronic Circuits and systems ◽

10.1109/ddecs.2006.1649575 ◽

2006 ◽

Cited By ~ 4

Author(s):

V.V. Belkin ◽

S.G. Sharshunov

Keyword(s):

Test Generation ◽

Functional Test ◽

Self Test

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Efficient test generation for built-in self-test boundary-scan template

10.1109/vtest.1991.208171 ◽

2002 ◽

Author(s):

P. Nagvajara ◽

M.G. Karpovsky ◽

L.B. Levitin

Keyword(s):

Test Generation ◽

Boundary Scan ◽

Efficient Test ◽

Self Test ◽

Built In Self Test

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