New Fault Models and Self-Test Generation for Microprocessors Using High-Level Decision Diagrams

2015 IEEE 18th International Symposium on Design and Diagnostics of Electronic Circuits & Systems ◽

10.1109/ddecs.2015.56 ◽

2015 ◽

Cited By ~ 3

Author(s):

Artjom Jasnetski ◽

Jaan Raik ◽

Anton Tsertov ◽

Raimund Ubar

Keyword(s):

Test Generation ◽

Decision Diagrams ◽

Fault Models ◽

Self Test ◽

High Level

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Software-based self-test generation for microprocessors with high-level decision diagrams

Proceedings of the Estonian Academy of Sciences ◽

10.3176/proc.2014.1.08 ◽

2014 ◽

Vol 63 (1) ◽

pp. 48 ◽

Cited By ~ 5

Author(s):

A Jasnetski ◽

R Ubar ◽

A Tsertov ◽

M Brik

Keyword(s):

Test Generation ◽

Decision Diagrams ◽

Self Test ◽

High Level

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Software-based self-test generation for microprocessors with high-level decision diagrams

2014 15th Latin American Test Workshop - LATW ◽

10.1109/latw.2014.6841923 ◽

2014 ◽

Cited By ~ 5

Author(s):

Raimund Ubar ◽

Anton Tsertov ◽

Artjom Jasnetski ◽

Marina Brik

Keyword(s):

Test Generation ◽

Decision Diagrams ◽

Self Test ◽

High Level

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On automatic software-based self-test program generation based on high-level decision diagrams

2016 17th Latin-American Test Symposium (LATS) ◽

10.1109/latw.2016.7483357 ◽

2016 ◽

Cited By ~ 3

Author(s):

Artjom Jasnetski ◽

Raimund Ubar ◽

Anton Tsertov

Keyword(s):

Decision Diagrams ◽

Test Program ◽

Program Generation ◽

Automatic Software ◽

Self Test ◽

High Level

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Probabilistic equivalence checking based on high-level decision diagrams

14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems ◽

10.1109/ddecs.2011.5783130 ◽

2011 ◽

Cited By ~ 2

Author(s):

Anton Karputkin ◽

Raimund Ubar ◽

Mati Tombak ◽

Jaan Raik

Keyword(s):

Equivalence Checking ◽

Decision Diagrams ◽

High Level

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Test generation, design-for-testability and built-in self-test for arithmetic units based on graph labeling

Journal of Electronic Testing ◽

10.1007/bf00135230 ◽

1991 ◽

Vol 2 (4) ◽

pp. 351-372 ◽

Cited By ~ 37

Author(s):

Abhijit Chatterjee ◽

Jacob A. Abraham

Keyword(s):

Test Generation ◽

Design For Testability ◽

Graph Labeling ◽

Self Test ◽

Arithmetic Units ◽

Built In Self Test

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High-level data path synthesis for built-in self-test designs

2001 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (IEEE Cat. No.01CH37233) ◽

10.1109/pacrim.2001.953577 ◽

2002 ◽

Author(s):

Laurence Tainruo Yang ◽

J. Muzio

Keyword(s):

Data Path ◽

Level Data ◽

Self Test ◽

Built In Self Test ◽

High Level ◽

Path Synthesis

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High Level Test Generation / SW based Embedded Test

14th Asian Test Symposium (ATS'05) ◽

10.1109/ats.2005.64 ◽

2005 ◽

Author(s):

P. Parvathala

Keyword(s):

Test Generation ◽

Embedded Test ◽

High Level

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Diagnostic Modelling of Digital Systems with Binary and High-Level Decision Diagrams

Progress in Industrial Mathematics at ECMI 2006 - Mathematics in Industry ◽

10.1007/978-3-540-71992-2_158 ◽

2008 ◽

pp. 902-907

Author(s):

Raimund Ubar ◽

Jaan Raik ◽

Helena Kruus ◽

Harri Lensen ◽

Teet Evartson

Keyword(s):

Digital Systems ◽

Decision Diagrams ◽

High Level

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High-Level Implementation-Independent Functional Software-Based Self-Test for RISC Processors

Journal of Electronic Testing ◽

10.1007/s10836-020-05856-7 ◽

2020 ◽

Vol 36 (1) ◽

pp. 87-103 ◽

Cited By ~ 1

Author(s):

Adeboye Stephen Oyeniran ◽

Raimund Ubar ◽

Maksim Jenihhin ◽

Jaan Raik

Keyword(s):

Self Test ◽

Functional Software ◽

High Level

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High Level Test Generation via Process Composition

Designing Correct Circuits - Workshops in Computing ◽

10.1007/978-1-4471-3544-9_6 ◽

1991 ◽

pp. 99-119

Author(s):

Venkatesh Akella ◽

Ganesh Gopalakrishnan

Keyword(s):

Test Generation ◽

High Level ◽

Process Composition

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