A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35μ CMOS technology

2006 ◽  
Author(s):  
M. Watanabe ◽  
F. Kobayashi
Keyword(s):  
Cmos Technology ◽  
Vlsi Chip ◽  
Gate Count ◽  
Gate Array

A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

1989 ◽  
Vol 24 (2) ◽  
pp. 380-387 ◽  
Author(s):  
F.-T. Liou ◽  
Y.-P. Han ◽  
F.R. Bryant ◽  
M. Zamanian
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gate Array

Optimized polysilicon CMOS technology for gate array applications

2002 ◽  
Author(s):  
E. Manea ◽  
C. Gingu ◽  
I. Cernica ◽  
F. Craciunoiu ◽  
S. Dunare ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Gate Array

scholarly journals Synthesis of composite logic gate in QCA embedding underlying regular clocking

2021 ◽  
Vol 34 (1) ◽  
pp. 115-131
Author(s):  
Jayanta Pal ◽  
Dhrubajyoti Bhowmik ◽  
Ayush Singh ◽  
Apu Saha ◽  
Bibhash Sen
Keyword(s):  
Symmetric Functions ◽  
Logic Gate ◽  
Logic Gates ◽  
Cmos Technology ◽  
Dissipated Energy ◽  
Circuit Realization ◽  
Alternative Technologies ◽  
Gate Count ◽  
Majority Voter ◽  
Cost Efficient

Quantum-dot Cellular Automata (QCA) has emerged as one of the alternative technologies for current CMOS technology. It has the advantage of computing at a faster speed, consuming lower power, and work at Nano- Scale. Besides these advantages, QCA logic is limited to its primitive gates, majority voter and inverter only, results in limitation of cost-efficient logic circuit realization. Numerous designs have been proposed to realize various intricate logic gates in QCA at the penalty of non-uniform clocking and improper layout. This paper proposes a Composite Gate (CG) in QCA, which realizes all the essential digital logic gates such as AND, NAND, Inverter, OR, NOR, and exclusive gates like XOR and XNOR. Reportedly, the proposed design is the first of its kind to generate all basic logic in a single unit. The most striking feature of this work is the augmentation of the underlying clocking circuit with the logic block, making it a more realistic circuit. The Reliable, Efficient, and Scalable (RES) underlying regular clocking scheme is utilized to enhance the proposed design?s scalability and efficiency. The relevance of the proposed design is best cited with coplanar implementation of 2-input symmetric functions, achieving 33% gain in gate count and without any garbage output. The evaluation and analysis of dissipated energy for both the design have been carried out. The end product is verified using the QCADesigner2.0.3 simulator, and QCAPro is employed for the study of power dissipation.

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