A 0.8- mu m CMOS technology for high-performance ASIC memory and channelless gate array

1989 ◽  
Vol 24 (2) ◽  
pp. 380-387 ◽  
Author(s):  
F.-T. Liou ◽  
Y.-P. Han ◽  
F.R. Bryant ◽  
M. Zamanian
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gate Array

A 0.8 mu m CMOS technology for high performance ASIC memory and channelless gate array

2003 ◽  
Author(s):  
F.T. Liou ◽  
Y.P. Han ◽  
F. Bryant ◽  
R. Miller ◽  
S.W. Chiu ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gate Array

scholarly journals High Area-Efficient Parallel Encoder with Compatible Architecture for 5G LDPC Codes

Symmetry ◽  
2021 ◽  
Vol 13 (4) ◽  
pp. 700
Author(s):  
Yufei Zhu ◽  
Zuocheng Xing ◽  
Zerun Li ◽  
Yang Zhang ◽  
Yifan Hu
Keyword(s):  
High Performance ◽  
Ldpc Codes ◽  
Low Complexity ◽  
Cmos Technology ◽  
Area Efficiency ◽  
Prior Art ◽  
New Radio ◽  
High Area ◽  
Significant Area ◽  
Area Efficient

This paper presents a novel parallel quasi-cyclic low-density parity-check (QC-LDPC) encoding algorithm with low complexity, which is compatible with the 5th generation (5G) new radio (NR). Basing on the algorithm, we propose a high area-efficient parallel encoder with compatible architecture. The proposed encoder has the advantages of parallel encoding and pipelined operations. Furthermore, it is designed as a configurable encoding structure, which is fully compatible with different base graphs of 5G LDPC. Thus, the encoder architecture has flexible adaptability for various 5G LDPC codes. The proposed encoder was synthesized in a 65 nm CMOS technology. According to the encoder architecture, we implemented nine encoders for distributed lifting sizes of two base graphs. The eperimental results show that the encoder has high performance and significant area-efficiency, which is better than related prior art. This work includes a whole set of encoding algorithm and the compatible encoders, which are fully compatible with different base graphs of 5G LDPC codes. Therefore, it has more flexible adaptability for various 5G application scenarios.

Molecular Simulation on Interfacial Structure and Gettering Efficiency of Si (110)/(100) Directly Bonded Hybrid Crystal Orientation Substrates

2009 ◽  
Vol 156-158 ◽  
pp. 199-204
Author(s):  
Hiroaki Kariyazaki ◽  
Tatsuhiko Aoki ◽  
Kouji Izunome ◽  
Koji Sueoka
Keyword(s):  
Molecular Simulation ◽  
Wafer Bonding ◽  
Crystal Orientation ◽  
High Performance ◽  
Cmos Technology ◽  
Experimental Results ◽  
Interfacial Structure ◽  
Atomic Configuration ◽  
Promising Technology ◽  
Bonded Interface

Hybrid crystal orientation technology (HOT) substrates comprised of Si (100) and (110) surface orientation paralleling each <110> direction attract considerable attentions as one of the promising technology for high performance bulk CMOS technology. Although HOT substrates are fabricated by wafer bonding of Si (110) and Si (100) surfaces, it is not clear the atomic configuration of interfacial structure. Furthermore, the possibility for the interface to be an effective gettering source of impurity metals was not well studied. In this paper, we studied the interfacial structure and gettering efficiency of the atomic bonded interface by molecular simulations. The results indicate that the simulated atomic configuration and gettering efficiency of the bonded interface agreed well with the experimental results.

An Offset Reduction Technique for Latch Type Sense Amplifier in High Performance and High Density SRAM

2012 ◽  
Vol 542-543 ◽  
pp. 769-774
Author(s):  
Qun Ling Yu ◽  
Na Bai ◽  
Yan Zhou ◽  
Rui Xing Li ◽  
Jun Ning Chen ◽  
...  
Keyword(s):  
High Performance ◽  
Circuit Simulation ◽  
Cmos Technology ◽  
Optimal Operation ◽  
Reduction Technique ◽  
Total Speed ◽  
Sense Amplifier ◽  
Simulation Results ◽  
A New Technique ◽  
Total Energy Dissipation

A new technique for reducing the offset of latch-type sense amplifier has been proposed and effect of enable signal voltage upon latch-type sense amplifier offset in SRAM has been investigated in this paper. Circuit simulation results on both StrongARM and Double-tail topologies show that the standard deviation of offset can be reduced by 31.23% (StrongARM SA) and 25.2% (Double-tail SA) , respectively, when the voltage of enable signal reaches 0.6V in TSMC 65nm CMOS technology. For a column of bit-cell (1024 bit-cell), the total speed is improved by 14.98% (StrongARAM SA) and 22.26% (Double-tail SA) at the optimal operation point separately, and the total energy dissipation is reduced by 30.45% and 29.47% with this scheme.

Copper Ulsi Interconnect Technology

1998 ◽  
Vol 514 ◽  
Author(s):  
D. Edelstein
Keyword(s):  
High Performance ◽  
Stress Testing ◽  
Cmos Technology ◽  
Functional Verification ◽  
Functional Modules ◽  
Mos Devices ◽  
Potential Problems ◽  
Cu Contamination ◽  
Interconnect Technology ◽  
Better Than

ABSTRACTRecently IBM announced the first implementation of full copper ULSI wiring in a CMOS technology, to be manufactured on its high-performance 0.22 um CMOS products this year. Features of this technology will be presented, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data will be presented fom all aspects of this testing, ranging from experiments designed to promote Cu contamination of the MOS devices, to temperature/humidity/bias stressing of assembled functional modules. The results in all areas are shown to be equal to or better than standards set by our current AI(Cu)/Wstud technology. This demonstrates that the potential problems associated with copper wiring that have long been discussed can be overcome.

A high-performance sub-half micron CMOS technology for fast SRAMs

2003 ◽  
Author(s):  
J. Hayden ◽  
F. Baker ◽  
S. Ernst ◽  
B. Jones ◽  
J. Klein ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology

New RP-CVD grown ultra-high performance selectively B-doped pure-Ge 20 nm QWs on (100)Si as basis material for post-Si CMOS technology

2013 ◽  
Vol 11 (1) ◽  
pp. 61-64 ◽  
Author(s):  
O. A. Mironov ◽  
A. H. A. Hassan ◽  
M. Uhlarz ◽  
S. Kiatgamolchai ◽  
A. Dobbie ◽  
...  
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Basis Material ◽  
20 Nm

scholarly journals Growth of high-quality semiconducting tellurium films for high-performance p-channel field-effect transistors with wafer-scale uniformity

2022 ◽  
Vol 6 (1) ◽  
Author(s):  
Taikyu Kim ◽  
Cheol Hee Choi ◽  
Pilgyu Byeon ◽  
Miso Lee ◽  
Aeran Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Physical Vapor Deposition ◽  
High Performance ◽  
Supply Voltage ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Three Dimensional ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Wafer Scale

AbstractAchieving high-performance p-type semiconductors has been considered one of the most challenging tasks for three-dimensional vertically integrated nanoelectronics. Although many candidates have been presented to date, the facile and scalable realization of high-mobility p-channel field-effect transistors (FETs) is still elusive. Here, we report a high-performance p-channel tellurium (Te) FET fabricated through physical vapor deposition at room temperature. A growth route involving Te deposition by sputtering, oxidation and subsequent reduction to an elemental Te film through alumina encapsulation allows the resulting p-channel FET to exhibit a high field-effect mobility of 30.9 cm2 V−1 s−1 and an ION/OFF ratio of 5.8 × 105 with 4-inch wafer-scale integrity on a SiO2/Si substrate. Complementary metal-oxide semiconductor (CMOS) inverters using In-Ga-Zn-O and 4-nm-thick Te channels show a remarkably high gain of ~75.2 and great noise margins at small supply voltage of 3 V. We believe that this low-cost and high-performance Te layer can pave the way for future CMOS technology enabling monolithic three-dimensional integration.

scholarly journals High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell

2021 ◽  
pp. 263-269
Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa
Keyword(s):  
High Speed ◽  
High Performance ◽  
Full Adder ◽  
Cmos Technology ◽  
Power Performance ◽  
High Speed Design ◽  
Power Delay Product ◽  
Full Swing ◽  
Output Swing ◽  
High Output

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.

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