An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit

2005 ◽  
Author(s):  
M. Watanabe ◽  
F. Kobayashi
Keyword(s):  
Dynamic Reconfiguration ◽  
Vlsi Chip ◽  
Gate Array

Multiple Faults Detection with SoC Dynamic Reconfiguration System Based on FPGA

2013 ◽  
Vol 694-697 ◽  
pp. 2642-2645 ◽  
Author(s):  
Cong Wang ◽  
Yi Long Liu ◽  
Peng Long Jiang ◽  
Qing Zhen Zhang ◽  
Fei Tao ◽  
...  
Keyword(s):  
Field Programmable Gate Array ◽  
Dynamic Reconfiguration ◽  
System On Chip ◽  
Detection Time ◽  
Software Platform ◽  
Multiple Faults ◽  
Field Programmable ◽  
Gate Array ◽  
On Chip

Multiple faults detection has great significance in practice. A dynamic reconfiguration SoC (System on Chip) system based on FPGA (Field Programmable Gate Array) is designed to realize multiple faults detection and reduce the detection time. Also, a framework of software platform and a case study for demonstrating and validating the SoC dynamic reconfiguration system are proposed.

Heat Diffusion in an Optical Logic Gate Array on Silicon-on-Sapphire

1997 ◽  
Vol 7 (3) ◽  
pp. 739-748
Author(s):  
H. Gualous ◽  
A. Koster ◽  
D. Pascal ◽  
S. Laval
Keyword(s):  
Logic Gate ◽  
Heat Diffusion ◽  
Optical Logic ◽  
Optical Logic Gate ◽  
Gate Array

A New High-Density 10T CMOS Gate-Array Base Cell for Two-Port SRAM Applications

2016 ◽  
Vol E99.C (6) ◽  
pp. 717-726
Author(s):  
Nobutaro SHIBATA ◽  
Yoshinori GOTOH ◽  
Takako ISHIHARA
Keyword(s):  
High Density ◽  
Gate Array
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